[Bug 105331] Dithering doesn't work on HD4600 when using DP

[bugzilla-daemon at bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=105331

--- Comment #12 from Mario Kleiner <mario.kleiner at tuebingen.mpg.de> ---
Black screens are not good, but degrading lots of well working displays out
there isn't either. And 6 bpc for VGA and DVI sinks can not be right.

I think our general EDID handling needs a little bit of improvement for EDID <
1.4, or your patch would need to be more selective wrt. what kind of sink is
connected to DP, or we need some manual override, otherwise this will be pretty
bad for lots of scientific users. It will practically brick their systems for
the purpose for which they bought them if they depend on DP->DVI/VGA output,
which many do. The patch has reached stable distro via kernel updates.

CRT monitors or other analog VGA driven displays have essentially infinite
resolution due to the analog input signal - only limited by the DAC resolution
at the source. Currently our drm_add_display_info() routine in drm_edid.c
assumes "unknown bpc" for any analog source, with the code comment "driver
figures it out in this case". I'd assume driving the VGA sink with the highest
bpc the hw can deliver should be safe, so assigning a large bpc, e.g., >= 16
bits would deal with analog sinks.

I also googled around a bit and found pdf's with descriptions of different EDID
versions, the DVI spec and its predecessor, the DFP 1.x spec. As far as my
understanding of EDID 1.3 from that goes, for a digital sink, if bit 0 of byte
0x14 is set to 1 (or for us: if (edid->input &  DRM_EDID_DIGITAL_TYPE_DVI) )
then the sink is a "DFP 1.x compatible TMDS" and that seems to mean that the
display can take 8 bpc / 24 bpp input signals. From
https://www.tu-chemnitz.de/informatik/RA/news/stack/kompendium/vortraege_99/peripherie/standards/dfp/DFP.pdf
section 3.10 "EDID support":

"If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.) without extensions,
the host will make the following assumptions:

1. 24-bit MSB-aligned RGB TFT
2. DE polarity is active high
3. H and V syncs are active high
4. Established CRT timings will be used
5. Dithering will not be enabled on the host
"

The DVI spec has similar wording wrt. DVI signals being compatible with DFP
sinks and 24 bits per pixel input signal support as mandatory.

My proposal would be a patch, also for stable, to assign info->bpc = 16 for
analog sinks instead of 0 and info->bpc = 8 if ((info->bpc == 0) &&
(edid->input &  DRM_EDID_DIGITAL_TYPE_DVI)) at the end of EDID 1.3 parsing.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
You are the assignee for the bug.