[Bug 97965] [BSW] External HDMI monitor suddenly shows solid color when playing Youtube video at 1080p [fifo underrun]

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=97965

--- Comment #31 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
(In reply to Yu Kang Ku from comment #30)
> In intel_display.c, there is one difference between valleyview_set_cdclk()
> and cherryview_set_cdclk() that seems rather interesting.  The following
> snippet is in valleyview_set_cdclk() but NOT in cherryview_set_cdclk():
> 
>         /* adjust self-refresh exit latency value */
>         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
>         val &= ~0x7f;
> 
>         /*
>          * For high bandwidth configs, we set a higher latency in the bunit
>          * so that the core display fetch happens in time to avoid underruns.
>          */
>         if (cdclk == 400000)
>                 val |= 4500 / 250; /* 4.5 usec */
>         else
>                 val |= 3000 / 250; /* 3.0 usec */
>         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
> 
> 
> Is this snippet applicable to BSW?

The register does exist there as well. It might be something play around with.
You can do so with the intel_reg tool easily, eg. "intel_reg read bunit:0x11",
"intel_reg write bunit:0x11 <value>".

On my BSW the value is  bunit:0x00000011 (0x03:0x00000011): 0x05804816
I didn't check whether the Punit or someone else adjusts that value at runtime.

This is what the register contains
EXIT_SELF_REFRESH_LATENCY       6:0
Exit Self Refresh Latency: Required latency to Exit Self Refresh in 250ns
increments. Default is 3uSec. PnP: This depends on SR exit+ data return for an
urgent ISOC request when dram is in SR. But SR exit latency depends on PM
opcode, setting it to h'24 i.e. 9us exit latency

RESERVED_2                      7:7

SCHEDULER_LATENCY               11:8
Scheduler Latency: Request latency that is considered as a Hi-Priority Request
for ISOC requests. Value programmed has 250ns resolution. Default is 2uSec.

ENTER_SELF_REFRESH_DLY          17:12
Enter Self Refresh Delay: Number of 250ns pulses the Bunit waits before
entering Self Refresh. Note: should not be set to less than 2 when dynamic SR
is enabled, otherwise the system may become unresponsive.

SR_EXIT_SYNC_EN                 18:18
Set this bit will prevent the Bunit get into SR if BRAM is full and high
priority requests blocked at badmit.

RESERVED_1                      21:19

ENTER_SELF_REFRESH_THRSH        31:22
Enter Self Refresh Threshold: Required request latency to enter self refresh.
If the Bunit receives ISOC requests that have a required latency less than this
value the Bunit will keep the Dunit out of Self Refresh.

Actually bits 31:22 look fairly interesting here. But perhaps start
experimenting with bits 6:0 a bit instead, since that's what we do on VLV as
well.

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