[Bug 100572] [SKL dmc] Headless mode media transcoding is 20-30% slower comparing to connected monitor use case

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=100572

--- Comment #10 from Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> ---
(In reply to Tvrtko Ursulin from comment #9)
> (In reply to Imre Deak from comment #7)
> > (In reply to Tvrtko Ursulin from comment #6)
> > > I tried not loading the DMC firmware and can confirm that the issue is not
> > > present in that case.
> > > 
> > > Also, it is possible to reproduce this in the default kernel config (no
> > > pinning is required) simply with igt/benchmarks/gem_latency -n 0 in which
> > > case the perf difference between the two setups was ~8x in my testing.
> > 
> > One possibility is that DC6 enables deeper system level power states and
> > this causes latency elsewhere. What are the PC state residencies shown by
> > powertop or the kernel's tools/power/x86/turbostat when DMC is loaded and
> > not?
> 
> 1. With DMC, idle system, no displays:
> 
> PKG is in PC2, CPU is in C7, GPU is in RC6.
> 
> When looking in i915_dmc_info I can see that the "DC3 - > DC5" transition
> counter increases exactly by one each second. "DC5 -> DC6 counter is zero".
> 
> If I now run gem_latency -n 0:
> 
> "DC3 -> DC5" counter starts increasing by ~2k per second.
> 
> PKG is not any deeper states now.

"not in" !

> CPU split between C2/C3/C6/C7 is approx. 42/2/10/40%.
> GPU is 0% RC6.
> 
> Benchmark goes slow.
> 
> 2. Now I force turn on a display (echo on | 
> tee /sys/class/drm/card0-HDMI-A-1/status).
> 
> "DC3 -> DC5" transition counter stops increasing.
> 
> PKG is still in PC2, CPU in C7 and GPU in RC6.
> 
> Benchmark is not normal speed and while it is running PKG is not in any low

s/not/now/ :( So it is normal speed now!

> power states, RC6 is 0% and CPU C2/C3/C6/C7 is approx 52/0/0/25%.
> 
> 3. DMC not loaded, idle system, no displays
> 
> PKG is now in PC7 (not PC2 as above!), CPU is C7, GPU is RC6.
> 
> gem_latency is now normal speed with power states like above.
> 
> Out of curiosity I tried forcing the display on in this config. That makes
> the PKG go to ~3% PC2, rest in PC7. Turning it off again brings it back to
> <0.5% PC2 and the rest in PC7.
>  
> > What's the effect of limiting max_cstates to 0 (and having DMC loaded)?
> 
> No effect on benchmark speed or reported "DC3 -> DC5" transitions.
> 
> > An other problem could be that the GPU is trying to access the display,
> > (maybe checking scan line counts or something?).
> 
> You mean something behind the covers or explicitly by i915?
>  
> > Does /sys/kernel/debug/dri/0/i915_dmc_info show any transitions during the
> > test when DMC is loaded?
> 
> Yes, see above. :)

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