[Bug 100144] [ILK][BAT] gem_exec_fence at await-hang-default.html

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=100144

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|REOPENED                    |RESOLVED

--- Comment #8 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit e6ba9992de6c63fe86c028b4876338e1cb7dac34
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Tue Apr 25 14:00:49 2017 +0100

    drm/i915: Differentiate between sw write location into ring and last hw
read

    We need to keep track of the last location we ask the hw to read up to
    (RING_TAIL) separately from our last write location into the ring, so
    that in the event of a GPU reset we do not tell the HW to proceed into
    a partially written request (which can happen if that request is waiting
    for an external signal before being executed).

    v2: Refactor intel_ring_reset() (Mika)

    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100144
    Testcase: igt/gem_exec_fence/await-hang
    Fixes: 821ed7df6e2a ("drm/i915: Update reset path to fix incomplete
requests")
    Fixes: d55ac5bf97c6 ("drm/i915: Defer transfer onto execution timeline to
actual hw submission")
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
    Cc: Mika Kuoppala <mika.kuoppala at intel.com>
    Link:
http://patchwork.freedesktop.org/patch/msgid/20170425130049.26147-1-chris@chris-wilson.co.uk
    Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

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