[Bug 100755] [HSW] linux next-20170407+ boots to a blank screen

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=100755

--- Comment #24 from Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> ---
(In reply to Jani Nikula from comment #21)
> (In reply to Dhinakaran Pandiyan from comment #20)
> > The rounding should not change anything. In the attachment (next-20170324
> > with fastboot=1, shows suspend/resume, works fine) bios programs link_m:
> > 134903 whereas driver programs link_m: 134567  and both work fine. This
> > shows the sink is able to recover even with small changes in the values. I
> > think, it's the bigger change in the down scaled values of link_m and link_n
> > that seems to have caused the problem.
> 
> No, this is a false conclusion, as the BIOS uses a different pixel clock.
You are right, but if you look at the link_m and pixel_rate values for the
first kernel modeset:

BIOS
[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n:
8388608, link_m: 134903, link_n: 524288, tu: 64
[drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 720x400, pixel
rate 69472

Kernel - before suspend-resume
[drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw
270000 pixel clock 69300KHz
[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n:
8388608, link_m: 134903, link_n: 524288, tu: 64
-> Regenerated pixel clock - 69472.904205322


Kernel - after suspend-resume
[drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw
270000 pixel clock 69300KHz
[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2422210, gmch_n:
8388608, link_m: 134567, link_n: 524288, tu: 64
-> Regenerated pixel clock - 69299.869537354

It does look like the sink can tolerate small differences in link_m for the
same pixel clock.

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