[Bug 101109] [IGT] [SKL/BDW/IVB/KBL] kms_mmap_write_crc test assertion failure

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=101109

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #13 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit b8f55be64453ea77fc51bff6cd0d906d18ce1cd2
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Aug 11 12:11:16 2017 +0100

    drm/i915: Split obj->cache_coherent to track r/w

    Another month, another story in the cache coherency saga. This time, we
    come to the realisation that i915_gem_object_is_coherent() has been
    reporting whether we can read from the target without requiring a cache
    invalidate; but we were using it in places for testing whether we could
    write into the object without requiring a cache flush. So split the
    tracking into two, one to decide before reads, one after writes.

    See commit e27ab73d17ef ("drm/i915: Mark CPU cache as dirty on every
    transition for CPU writes") for the previous entry in this saga.

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