[Bug 103705] [BAT] igt at gem_workarounds@basic-read - Failed assertion: workaround_fail_count(fd, ctx) == 0
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Tue Nov 14 15:34:59 UTC 2017
https://bugs.freedesktop.org/show_bug.cgi?id=103705
Chris Wilson <chris at chris-wilson.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #1 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit 34991bd48c927712678d0cea77628328f9046923
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sat Nov 11 10:03:36 2017 +0000
drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl
gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't
sticking. Commit 0a60797a0efb ("drm/i915: Implement
ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a
masked register in the context image, but commit 90007bca6162
("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as
an ordering unmasked register. The masked write will be losing the
default settings if we trust the original commit. That gem_workarounds
reports the value is lost entirely is more worrying though -- but it
clearly suggests that it is not a masked register in the context image,
so unify both w/a to use the original rmw.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103705
Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.")
References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake
Workarounds.")
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Rafael Antognolli <rafael.antognolli at intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Cc: Oscar Mateo <oscar.mateo at intel.com>
Cc: Mika Kuoppala <mika.kuoppala at intel.com>
Cc: Jani Nikula <jani.nikula at linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/20171111100336.11020-1-chris@chris-wilson.co.uk
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
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