[Bug 102373] [CI][SNB] *ERROR* CPU pipe [A|B] FIFO underrun

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=102373

--- Comment #9 from Marta Löfstedt <marta.lofstedt at intel.com> ---
A new trend of 100% reproducibility on:
igt at kms_busy@extended-pageflip-hang-oldfb-render-B and 
igt at kms_cursor_crc@cursor-128x128-dpms

appear to have started at CI_DRM_3242:

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3242/shard-snb5/igt@kms_busy@extended-pageflip-hang-oldfb-render-B.html
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3242/shard-snb4/igt@kms_cursor_crc@cursor-128x128-dpms.html

and is stable at hitting FIFO underrun until at least CI_DRM_3249.

I just noticed that igt at kms_busy@extended-pageflip-hang-oldfb-render-B and 
igt at kms_cursor_crc@cursor-128x128-dpms are scheduled in the same shard for all
those runs. The re-randomization of which test goes into which shard is only
done  when IGT is rebuilt. 

Note, for each CI_DRM_NNNN there is a shards.html, where easily can see which
tests that are in which shards, example:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3246/shards.html

So, there is potentially some context leak causing this grouping of FIFO
underruns being more probable when tests are run in the same shard.

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