[Bug 102937] [GLK-RVP]/[APL-Electro]HDA verb command response timedout; board to board variation with same S/W

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=102937

--- Comment #8 from Abhay Kumar <abhay.kumar at intel.com> ---
https://cgit.freedesktop.org/drm/drm-tip/tree/drivers/gpu/drm/i915/intel_cdclk.c

we are not entering into func "intel_crtc_compute_min_cdclk"

if (intel_crtc_has_dp_encoder(crtc_state) &&
            crtc_state->has_audio &&
            crtc_state->port_clock >= 540000 &&
            crtc_state->lane_count == 4) {
                if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
                        /* Display WA #1145: glk,cnl */
                        min_cdclk = max(316800, min_cdclk);
                } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
                        /* Display WA #1144: skl,bxt */
                        min_cdclk = max(432000, min_cdclk);
                }
        }


Looks like it will only enter inside for HBR2 and not for HBR or RBR.

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