[Bug 97244] [DP] [SKL] 5k tiled dual DP (two-pipe, two-port) display sync issues

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=97244

--- Comment #33 from Ross Bishop <rossbishop at live.co.uk> ---
I'm also in the UP2715K boat with screen corruption.

There's a range of software which appears to provide information about PCI
devices. I've been looking at PCIScope, it gives you access to the PCI
registers and there is a dump facility.

I'm brand new to PCI though and I don't know how to translate the base address
to the actual location of the MMIO registers. It feels like there's far too
little information in the dump tab.

http://envytools.readthedocs.io/en/latest/hw/mmio.html#gf100-mmio-map

Supposedly this page contains the Nvidia MMIO map for GF100 devies and onwards
(GP102 here). 

What are we actually looking for in this dump? It was mentioned but never
specified what can be found that would be helpful for achieving sync for the
two panel halves.

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