[Bug 100439] [GLK] cdclock frequency is always the same

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=100439

--- Comment #7 from Abhijeet Kumar <abhijeet.kumar at intel.com> ---
(In reply to Dhinakaran Pandiyan from comment #3)
> HDMI audio is being enabled, which restricts cdclk going lower than 2*Azalia
> bclk (96 MHz by default). The choices for cdclk on GLK are 316.8 MHz, 158.4
> MHz and 79.2 MHz. So, the only value greater than 2*96 MHz is 316.8 MHz.
> 
> From BSpec
> "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96
> MHz)
> 316.8 MHz CD
> 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single
> pipe eDP/MIPI configurations, no audio support)"
> 
> Not entirely sure what happens if we violate this restriction in practice,

Adding my two cents to it. Due to violation I've seen igt tests at pm_rpm,kms at flip
failing as HDA was not suspending.

Test name
kms_flip --run-subtest vblank-vs-modeset-rpm
kms_flip --run-subtest vblank-vs-modeset-rpm-interruptible
kms_flip --run-subtest vblank-vs-dpms-rpm
kms_flip --run-subtest vblank-vs-dpms-rpm-interruptible
pm_rpm --run-subtest basic-pci-d3-state
pm_rpm --run-subtest basic-rte

> but I think it makes sense to define a new API to get the actual Azalia bclk
> from the audio driver and explore options to lower that.

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