[Bug 104982] [IGT][CNL Only] igt at debugfs_test@read_all_entries dmesg-warn WARN_ON_ONCE(mcr & ((((3) & 3) << 26) | (((3) & 3) << 24)))

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=104982

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|INVALID                     |FIXED

--- Comment #14 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit 1e40d4aea57bbbd277777dd1fe18599dd77c55ab
Author: Yunwei Zhang <yunwei.zhang at intel.com>
Date:   Fri May 18 15:39:57 2018 -0700

    drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads

    WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
    read into Slice/Subslice specific registers, MCR packet control
    register(0xFDC) needs to be programmed to point to any enabled
    slice/subslice pair. Otherwise, incorrect value will be returned.

    However, that means each subsequent MMIO read will be forwarded to a
    specific slice/subslice combination as read is unicast. This is OK since
    slice/subslice specific register values are consistent in almost all cases
    across slice/subslice. There are rare occasions such as INSTDONE that this
    value will be dependent on slice/subslice combo, in such cases, we need to
    program 0xFDC and recover this after. This is already covered by
    read_subslice_reg.

    Also, 0xFDC will lose its information after TDR/engine reset/power state
    change.

    References: HSD#1405586840, BSID#0575

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