[Bug 109611] New: [CI][DRMTIP] igt at gem_pwrite_pread@snooped-copy-performance - incomplete
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Tue Feb 12 07:42:25 UTC 2019
https://bugs.freedesktop.org/show_bug.cgi?id=109611
Bug ID: 109611
Summary: [CI][DRMTIP]
igt at gem_pwrite_pread@snooped-copy-performance -
incomplete
Product: DRI
Version: DRI git
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: DRM/Intel
Assignee: intel-gfx-bugs at lists.freedesktop.org
Reporter: lakshminarayana.vudum at intel.com
QA Contact: intel-gfx-bugs at lists.freedesktop.org
CC: intel-gfx-bugs at lists.freedesktop.org
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_216/fi-icl-y/igt@gem_pwrite_pread@snooped-copy-performance.html
177.574455] [IGT] kms_vblank: exiting, ret=0
<7>[ 177.596382] [drm:intel_atomic_check [i915]] [CONNECTOR:190:DP-1] Limiting
display bpp to 18 instead of EDID bpp 18, requested bpp 36, max platform bpp 36
<7>[ 177.596465] [drm:intel_dp_compute_config [i915]] DP link computation with
max lane count 2 max rate 270000 max bpp 18 pixel clock 214000KHz
<7>[ 177.596537] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
<7>[ 177.596606] [drm:intel_dp_compute_config [i915]] DP lane count 2 clock
270000 bpp 18
<7>[ 177.596675] [drm:intel_dp_compute_config [i915]] DP link rate required
481500 available 540000
<7>[ 177.596744] [drm:intel_atomic_check [i915]] hw max bpp: 18, pipe bpp: 18,
dithering: 1
<7>[ 177.596813] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_hdisplay (expected 0, found 1920)
<7>[ 177.596877] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_htotal (expected 0, found 2104)
<7>[ 177.596939] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_hblank_start (expected 0, found 1920)
<7>[ 177.597000] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_hblank_end (expected 0, found 2104)
<7>[ 177.597059] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_hsync_start (expected 0, found 1936)
<7>[ 177.597122] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_hsync_end (expected 0, found 1952)
<7>[ 177.597247] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vdisplay (expected 0, found 1080)
<7>[ 177.597317] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vtotal (expected 0, found 1128)
<7>[ 177.597376] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vblank_start (expected 0, found 1080)
<7>[ 177.597435] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vblank_end (expected 0, found 1128)
<7>[ 177.597494] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vsync_start (expected 0, found 1083)
<7>[ 177.597551] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_vsync_end (expected 0, found 1097)
<7>[ 177.597732] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.flags (2) (expected 0, found 2)
<7>[ 177.597830] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.flags (8) (expected 0, found 8)
<7>[ 177.597920] [drm:pipe_config_err [i915]] mismatch in
base.adjusted_mode.crtc_clock (expected 0, found 214000)
<7>[ 177.598013] [drm:intel_dump_pipe_config [i915]] [CRTC:82:pipe A][modeset]
<7>[ 177.598082] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
<7>[ 177.598302] [drm:intel_dump_pipe_config [i915]] output format: RGB
<7>[ 177.598390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe
bpp: 18, dithering: 1
<7>[ 177.598452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m:
7479842, gmch_n: 8388608, link_m: 415546, link_n: 524288, tu: 64
<7>[ 177.598509] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
<7>[ 177.598563] [drm:intel_dump_pipe_config [i915]] requested mode:
<7>[ 177.598574] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90
214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7>[ 177.598629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
<7>[ 177.598637] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 90
214000 1920 1936 1952 2104 1080 1083 1097 1128 0x48 0xa
<7>[ 177.598697] [drm:intel_dump_pipe_config [i915]] crtc timings: 214000 1920
1936 1952 2104 1080 1083 1097 1128, type: 0x48 flags: 0xa
<7>[ 177.598754] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe
src size: 1920x1080, pixel rate 214000
<7>[ 177.598815] [drm:intel_dump_pipe_config [i915]] num_scalers: 2,
scaler_users: 0x0, scaler_id: -1
<7>[ 177.598875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos:
0x00000000, size: 0x00000000, disabled
<7>[ 177.598934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
<7>[ 177.599010] [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0:
0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0,
mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0,
mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0,
mg_pll_tdc_coldst_bias: 0x0
<7>[ 177.599084] [drm:intel_dump_pipe_config [i915]] planes on this crtc
<7>[ 177.599204] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 1A]
disabled, scaler_id = -1
<7>[ 177.599278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 2A]
disabled, scaler_id = -1
<7>[ 177.599352] [drm:intel_dump_pipe_config [i915]] [PLANE:44:plane 3A]
disabled, scaler_id = -1
<7>[ 177.599418] [drm:intel_dump_pipe_config [i915]] [PLANE:51:plane 4A]
disabled, scaler_id = -1
<7>[ 177.599487] [drm:intel_dump_pipe_config [i915]] [PLANE:58:plane 5A]
disabled, scaler_id = -1
<7>[ 177.599557] [drm:intel_dump_pipe_config [i915]] [PLANE:65:plane 6A]
disabled, scaler_id = -1
<7>[ 177.599624] [drm:intel_dump_pipe_config [i915]] [PLANE:72:plane 7A]
disabled, scaler_id = -1
<7>[ 177.599689] [drm:intel_dump_pipe_config [i915]] [PLANE:79:cursor A]
disabled, scaler_id = -1
<7>[ 177.599770] [drm:intel_atomic_check [i915]] New cdclk calculated to be
logical 307200 kHz, actual 307200 kHz
<7>[ 177.599834] [drm:intel_atomic_check [i915]] New voltage level calculated
to be logical 0, actual 0
<7>[ 177.599912] [drm:intel_find_shared_dpll [i915]] [CRTC:82:pipe A]
allocated DPLL 0
<7>[ 177.599976] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for
pipe A
<7>[ 177.600044] [drm:skl_compute_wm [i915]] [PLANE:30:plane 1A] ddb (0 - 0)
-> (0 - 992)
<7>[ 177.600095] [drm:skl_compute_wm [i915]] [PLANE:79:cursor A] ddb (0 - 0)
-> (992 - 1024)
<7>[ 177.600255] [drm:skl_compute_wm [i915]] [PLANE:132:cursor B] ddb (992 -
1024) -> (0 - 0)
<7>[ 177.600705] [drm:intel_disable_pipe [i915]] disabling pipe B
<7>[ 177.610078] [drm:intel_power_well_disable [i915]] disabling DDI A IO
<7>[ 177.610158] [drm:intel_power_well_disable [i915]] disabling AUX A
<7>[ 177.610216] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active
2, on? 1) for crtc 135
<7>[ 177.610268] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
<7>[ 177.610323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:189:DDI A]
<7>[ 177.610359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:194:DDI B]
<7>[ 177.610395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:196:DP-MST A]
<7>[ 177.610432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:197:DP-MST B]
<7>[ 177.610463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:198:DP-MST C]
<7>[ 177.610497] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
<7>[ 177.610541] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
<7>[ 177.610579] [drm:verify_single_dpll_state.isra.105 [i915]] TBT PLL
<7>[ 177.610616] [drm:verify_single_dpll_state.isra.105 [i915]] MG PLL 1
<7>[ 177.610652] [drm:verify_single_dpll_state.isra.105 [i915]] MG PLL 2
<7>[ 177.610688] [drm:verify_single_dpll_state.isra.105 [i915]] MG PLL 3
<7>[ 177.610723] [drm:verify_single_dpll_state.isra.105 [i915]] MG PLL 4
<7>[ 177.610773] [drm:intel_power_well_enable [i915]] enabling AUX A
<7>[ 177.610821] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active
1, on? 0) for crtc 82
<7>[ 177.610853] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
<7>[ 177.610981] [drm:intel_power_well_enable [i915]] enabling DDI A IO
<7>[ 177.611851] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET
value 0a
<7>[ 177.612277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7>[ 177.612311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis
level 0
<7>[ 177.612348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP
training pattern TPS1
<7>[ 177.613024] [drm:intel_dp_start_link_train [i915]] clock recovery OK
<7>[ 177.613061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP
training pattern TPS2
<7>[ 177.614066] [drm:intel_dp_start_link_train [i915]]
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