[Bug 108336] [CI][DRMTIP] igt@*crc tests* - warn / dmesg-warn - Suspicious CRC: it looks like the CRC read back was from a register in a powered down well

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=108336

--- Comment #10 from Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> ---
Here is more traces. I've added own prints to skl_program_plane,
skl_write_plane_wm, intel_update_crtc and others. Here you can see that at some
point we get ddb allocation updated from 0-0 to  0-992, also for level 0 there
should be 6 blocks, however in skl_write_plane_wm we write zeroes! 
Looks strange at least to me. Then immediately after that we start to get FIFO
underruns:

[  112.129891] skl compute wm
[  112.129892] skl compute wm work
[  112.129897] plane blocks per line 1048576 y_tile_minimum 4194304 cpp 4 min
scanlines 4 plane pixel rate 154000 wp->xtiled 0 ytiled 0 rc 0
[  112.129900] Level 0 blocks 6 lines 1 latency 3
[  112.129902] Level 1 blocks 33 lines 2 latency 22
[  112.129904] Level 2 blocks 33 lines 2 latency 22
[  112.129906] Level 3 blocks 49 lines 3 latency 32
[  112.129909] Level 4 blocks 49 lines 3 latency 32
[  112.129911] Level 5 blocks 129 lines 8 latency 100
[  112.129913] Level 6 blocks 177 lines 11 latency 148
[  112.129916] Level 7 blocks 193 lines 12 latency 160
[  112.130229] [PLANE:30:plane 1A] state 00000000cf256453 ddb (0 - 0) -> (0 -
992)
[  112.130518] [PLANE:79:cursor A] state 00000000cf256453 ddb (0 - 0) -> (992 -
1024)
[  112.131873] intel_update_crtc start
[  112.132571] skl update crc wm
[  112.132572] skl update crc wm work
[  112.132936] skl update crc wm
[  112.132937] skl update crc wm work
[  112.135853] skl_program plane start
[  112.135860] skl write plane wm
[  112.135868] Writing plane 0 level 0 6 blocks while plane ddb(0-992) enabled
[  112.135870] Writing plane 0 level 1 33 blocks while plane ddb(0-992) enabled
[  112.135872] Writing plane 0 level 2 33 blocks while plane ddb(0-992) enabled
[  112.135875] Writing plane 0 level 3 49 blocks while plane ddb(0-992) enabled
[  112.135877] Writing plane 0 level 4 49 blocks while plane ddb(0-992) enabled
[  112.135879] Writing plane 0 level 5 129 blocks while plane ddb(0-992)
enabled
[  112.135881] Writing plane 0 level 6 177 blocks while plane ddb(0-992)
enabled
[  112.135883] Writing plane 0 level 7 193 blocks while plane ddb(0-992)
enabled
[  112.135885] Writing plane 0 transition level 8 20 blocks while plane
ddb(0-992) enabled
[  112.135887] skl_program plane end
[  112.135890] skl write plane wm
[  112.135892] Writing plane 1 level 0 0 blocks while plane ddb(0-0) enabled
[  112.135894] Writing plane 1 level 1 0 blocks while plane ddb(0-0) enabled
[  112.135897] Writing plane 1 level 2 0 blocks while plane ddb(0-0) enabled
[  112.135898] Writing plane 1 level 3 0 blocks while plane ddb(0-0) enabled
[  112.135901] Writing plane 1 level 4 0 blocks while plane ddb(0-0) enabled
[  112.135903] Writing plane 1 level 5 0 blocks while plane ddb(0-0) enabled
[  112.135905] Writing plane 1 level 6 0 blocks while plane ddb(0-0) enabled
[  112.135907] Writing plane 1 level 7 0 blocks while plane ddb(0-0) enabled
[  112.135909] Writing plane 1 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.135912] skl write plane wm
[  112.135914] Writing plane 2 level 0 0 blocks while plane ddb(0-0) enabled
[  112.135916] Writing plane 2 level 1 0 blocks while plane ddb(0-0) enabled
[  112.135918] Writing plane 2 level 2 0 blocks while plane ddb(0-0) enabled
[  112.135920] Writing plane 2 level 3 0 blocks while plane ddb(0-0) enabled
[  112.135922] Writing plane 2 level 4 0 blocks while plane ddb(0-0) enabled
[  112.135924] Writing plane 2 level 5 0 blocks while plane ddb(0-0) enabled
[  112.135926] Writing plane 2 level 6 0 blocks while plane ddb(0-0) enabled
[  112.135928] Writing plane 2 level 7 0 blocks while plane ddb(0-0) enabled
[  112.135931] Writing plane 2 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.135933] skl write plane wm
[  112.135935] Writing plane 3 level 0 0 blocks while plane ddb(0-0) enabled
[  112.135937] Writing plane 3 level 1 0 blocks while plane ddb(0-0) enabled
[  112.135939] Writing plane 3 level 2 0 blocks while plane ddb(0-0) enabled
[  112.135941] Writing plane 3 level 3 0 blocks while plane ddb(0-0) enabled
[  112.135943] Writing plane 3 level 4 0 blocks while plane ddb(0-0) enabled
[  112.135945] Writing plane 3 level 5 0 blocks while plane ddb(0-0) enabled
[  112.135947] Writing plane 3 level 6 0 blocks while plane ddb(0-0) enabled
[  112.135949] Writing plane 3 level 7 0 blocks while plane ddb(0-0) enabled
[  112.135951] Writing plane 3 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.135954] skl write plane wm
[  112.135956] Writing plane 4 level 0 0 blocks while plane ddb(0-0) enabled
[  112.135958] Writing plane 4 level 1 0 blocks while plane ddb(0-0) enabled
[  112.135960] Writing plane 4 level 2 0 blocks while plane ddb(0-0) enabled
[  112.135962] Writing plane 4 level 3 0 blocks while plane ddb(0-0) enabled
[  112.135964] Writing plane 4 level 4 0 blocks while plane ddb(0-0) enabled
[  112.135966] Writing plane 4 level 5 0 blocks while plane ddb(0-0) enabled
[  112.135968] Writing plane 4 level 6 0 blocks while plane ddb(0-0) enabled
[  112.135971] Writing plane 4 level 7 0 blocks while plane ddb(0-0) enabled
[  112.135973] Writing plane 4 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.135975] skl write plane wm
[  112.135977] Writing plane 5 level 0 0 blocks while plane ddb(0-0) enabled
[  112.135979] Writing plane 5 level 1 0 blocks while plane ddb(0-0) enabled
[  112.135981] Writing plane 5 level 2 0 blocks while plane ddb(0-0) enabled
[  112.135983] Writing plane 5 level 3 0 blocks while plane ddb(0-0) enabled
[  112.135985] Writing plane 5 level 4 0 blocks while plane ddb(0-0) enabled
[  112.135987] Writing plane 5 level 5 0 blocks while plane ddb(0-0) enabled
[  112.135990] Writing plane 5 level 6 0 blocks while plane ddb(0-0) enabled
[  112.135991] Writing plane 5 level 7 0 blocks while plane ddb(0-0) enabled
[  112.135994] Writing plane 5 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.135996] skl write plane wm
[  112.135999] Writing plane 6 level 0 0 blocks while plane ddb(0-0) enabled
[  112.136001] Writing plane 6 level 1 0 blocks while plane ddb(0-0) enabled
[  112.136003] Writing plane 6 level 2 0 blocks while plane ddb(0-0) enabled
[  112.136005] Writing plane 6 level 3 0 blocks while plane ddb(0-0) enabled
[  112.136007] Writing plane 6 level 4 0 blocks while plane ddb(0-0) enabled
[  112.136008] Writing plane 6 level 5 0 blocks while plane ddb(0-0) enabled
[  112.136011] Writing plane 6 level 6 0 blocks while plane ddb(0-0) enabled
[  112.136013] Writing plane 6 level 7 0 blocks while plane ddb(0-0) enabled
[  112.136015] Writing plane 6 transition level 8 0 blocks while plane ddb(0-0)
enabled
[  112.136042] intel_update_crtc end
[  112.149925] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun

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