[Bug 109473] [CI][DRMTIP] igt at gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=109473

--- Comment #2 from Chris Wilson <chris at chris-wilson.co.uk> ---
We need to go harderer...

See commit a889580c087a9cf91fddb3832ece284174214183
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Dec 7 13:40:37 2018 +0000

    drm/i915: Flush GPU relocs harder for gen3

    Adding an extra MI_STORE_DWORD_IMM to the gpu relocation path for gen3
    was good, but still not good enough. To survive 24+ hours under test we
    needed to perform not one, not two but three extra store-dw. Doing so
    for each GPU relocation was a little unsightly and since we need to
    worry about userspace hitting the same issues, we should apply the dummy
    store-dw into the EMIT_FLUSH.

    Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
    References: 7fa28e146994 ("drm/i915: Write GPU relocs harder with gen3")
    Testcase: igt/gem_tiled_fence_blits # blb/pnv
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
    Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
    Link:
https://patchwork.freedesktop.org/patch/msgid/20181207134037.11848-1-chris@chris-wilson.co.uk

Suggests, if we can't actually find a reason for it, to bump the num_store_dw
used for the w/a

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