[Bug 30364] [945GME] poor 3d performance in deep c-states

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=30364

Ville Syrjala <ville.syrjala at linux.intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|WONTFIX                     |FIXED

--- Comment #79 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
I got fed up with my 945gm not being capabile of 60fps glxgears.

commit d938da6b132a2d6addeba4c57a67ec3c07824843
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Fri Mar 22 20:08:03 2019 +0200

    drm/i915: Disable C3 when enabling vblank interrupts on i945gm

The main difference compared to the older pm_qos attempts is that I found a way
to dig out the exact c3 disable latency, so we should have a reasonable
guarantee that we do disable c3 but not c2. The power cost of not using c3
seems to be about 0.7W on my machine (with the display on), so this isn't
exactly cheap :(

I did spend quite a bit of time at some point digging through the chipset docs
(such as they are). It's been a while since I did that but I'll try to
summarize what I recall; Gen3 introduced some kind of new mechanism by which
the gmch can wake up the CPU. The old AGPBUSY/PM_BUSY involved the ICH as well
IIRC, whereas the new mechanism supposedly does not. IIRC the new mechanism
already appears in the i915gm docs, but my theory is that i945gm is where it
actually got into use and either it is broken or we're missing some magic
undocumented bit somewhere. I did try (blindly if necessary) poking at various
registers that seemed relevant. Alas, I was unable to find a magic bit to make
C3+vblank interrupts cooperate.

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