[Bug 103191] [CI] igt at kms_pipe_crc_basic@* - fail - CRC mismatch

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=103191

--- Comment #34 from harish.chegondi at intel.com ---
I turned on the tracing for intel_pipe_crc and ran the tests. Below are few
lines from the trace:

intel_pipe_crc: pipe A, frame=64813, scanline=5  crc=0032abc8 001dcb91 001dcb91
001dcb91 004987da
intel_pipe_crc: pipe A, frame=64814, scanline=19 crc=00774d8d 0031d43b 0031d43b
0031d43b 003279d1
intel_pipe_crc: pipe A, frame=64815, scanline=19 crc=007956cd 001db1a2 001db1a2
001db1a2 005450f7
intel_pipe_crc: pipe A, frame=64816, scanline=18 crc=007956cd 001db1a2 001db1a2
001db1a2 005450f7
intel_pipe_crc: pipe A, frame=64817, scanline=17 crc=007956cd 001db1a2 001db1a2
001db1a2 005450f7
intel_pipe_crc: pipe A, frame=64818, scanline=21 crc=007956cd 001db1a2 001db1a2
001db1a2 005450f7

The traces are from display_pipe_crc_irq_handler function (code below) which
has comments that the first CRC on all CPUs and also the second CRC in GEN8+
CPUs are incorrect and hence skipped. From the above traces it appears that the
second CRC is incorrect even on Bay Trail. As an experiment, I skipped the
second CRC as well on all CPUs and now the CRC tests are passing. I will send
out a patch with this change.

static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
                                         enum pipe pipe,
                                         u32 crc0, u32 crc1,
                                         u32 crc2, u32 crc3,
                                         u32 crc4)
{
        struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
        struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
        u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };

        trace_intel_pipe_crc(crtc, crcs);

        spin_lock(&pipe_crc->lock);
        /*
         * For some not yet identified reason, the first CRC is
         * bonkers. So let's just wait for the next vblank and read
         * out the buggy result.
         *
         * On GEN8+ sometimes the second CRC is bonkers as well, so
         * don't trust that one either.
         */
        if (pipe_crc->skipped <= 0 ||
            (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
                pipe_crc->skipped++;
                spin_unlock(&pipe_crc->lock);
                return;
        }

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