[Bug 108773] i915.fastboot=1 is broken on Thinkpad S1 Yoga (Haswell)

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=108773

--- Comment #21 from Johannes Krampf <johannes.krampf at gmail.com> ---
I booted into the Arch Linux provided 5.1.3 kernel with module_blacklist=i915
on the kernel parameters and verified that there was no i915 in lsmod output.

Output of `intel_reg read 0x48250 0x48254 0x48350 0x48354 0x48360 0x48260
0x48264 0x48268 0x48400 0xc8250 0xc8254` without i915:

```
Error: /usr/share/igt-gpu-tools/registers/common_display.txt:1:
('CPU_VGACNTRL', '0x00041000', '')
Error: /usr/share/igt-gpu-tools/registers/haswell:1: common_display.txt
Warning: reading '/usr/share/igt-gpu-tools/registers/haswell' failed. Using
builtin register spec.
                   BLC_PWM_CPU_CTL2 (0x00048250): 0xe0000000 (enable 1, pipe
EDP, blinking 0, granularity 128)
                    BLC_PWM_CPU_CTL (0x00048254): 0x03540354 (cycle 852, freq
852)
                  BLC_PWM2_CPU_CTL2 (0x00048350): 0x60000000 (enable 0, pipe
EDP, blinking 0, granularity 128)
                   BLC_PWM2_CPU_CTL (0x00048354): 0x00000000 (cycle 0, freq 0)
                       BLC_MISC_CTL (0x00048360): 0x00000000 (PWM1-PCH
PWM2-CPU)
                                    (0x00048260): 0x00000002
                                    (0x00048264): 0x00000000
                                    (0x00048268): 0x00000000
                       UTIL_PIN_CTL (0x00048400): 0x00000000 (enable 0,
transcoder A, mode data, data 0 inverted polarity 0)
                   BLC_PWM_PCH_CTL1 (0x000c8250): 0x80000000 (enable 1,
override 0, inverted polarity 0)
                   BLC_PWM_PCH_CTL2 (0x000c8254): 0x03540354 (freq 852, cycle
852)
```

Values when running with the module i915 loaded:

```
Error: /usr/share/igt-gpu-tools/registers/common_display.txt:1:
('CPU_VGACNTRL', '0x00041000', '')
Error: /usr/share/igt-gpu-tools/registers/haswell:1: common_display.txt
Warning: reading '/usr/share/igt-gpu-tools/registers/haswell' failed. Using
builtin register spec.
                   BLC_PWM_CPU_CTL2 (0x00048250): 0x60000000 (enable 0, pipe
EDP, blinking 0, granularity 128)
                    BLC_PWM_CPU_CTL (0x00048254): 0x03540354 (cycle 852, freq
852)
                  BLC_PWM2_CPU_CTL2 (0x00048350): 0x60000000 (enable 0, pipe
EDP, blinking 0, granularity 128)
                   BLC_PWM2_CPU_CTL (0x00048354): 0x00000000 (cycle 0, freq 0)
                       BLC_MISC_CTL (0x00048360): 0x00000000 (PWM1-PCH
PWM2-CPU)
                                    (0x00048260): 0x00000001
                                    (0x00048264): 0x00000000
                                    (0x00048268): 0x00000000
                       UTIL_PIN_CTL (0x00048400): 0x00000000 (enable 0,
transcoder A, mode data, data 0 inverted polarity 0)
                   BLC_PWM_PCH_CTL1 (0x000c8250): 0xc0000000 (enable 1,
override 1, inverted polarity 0)
                   BLC_PWM_PCH_CTL2 (0x000c8254): 0x03540130 (freq 852, cycle
304)
```

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