[Bug 112147] [CI][BAT][hsw] igt at i915_selftest@live_blt - incoherency

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=112147

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from Chris Wilson <chris at chris-wilson.co.uk> ---
Just the normal stab in the dark, 

commit f9228f7658734fe16ef7eec554d187a3d9577be8 (HEAD -> drm-intel-next-queued,
drm-intel/drm-intel-next-queued)
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Mon Nov 11 12:09:57 2019 +0000

    drm/i915/gt: Try an extra flush on the Haswell blitter

    On gen7, including Haswell, the MI_FLUSH_DW command is not synchronous
    with the command streamer nor is there an option to make it so. To hide
    this we add a large delay on the CS so that the breadcrumb should always
    be visible before the interrupt. However, that does not seem to be
    enough to ensure the memory is actually coherent with the read of the
    breadcrumb. The breadcrumb update is a post-sync op... Throw in a
    preliminary MI_FLUSH_DW before the breadcrumb update in the hope that
    helps.

    References: https://bugs.freedesktop.org/show_bug.cgi?id=112147
    Testcase: igt/i915_selftest/live_blt
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Acked-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
    Link:
https://patchwork.freedesktop.org/patch/msgid/20191111120957.17732-1-chris@chris-wilson.co.uk

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