[Bug 112346] New: [CI][SHARDS]igt at i915_selftest@live_gt_mocs - incomplete - system hang
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Wed Nov 20 07:45:23 UTC 2019
https://bugs.freedesktop.org/show_bug.cgi?id=112346
Bug ID: 112346
Summary: [CI][SHARDS]igt at i915_selftest@live_gt_mocs -
incomplete - system hang
Product: DRI
Version: DRI git
Hardware: Other
OS: All
Status: NEW
Severity: not set
Priority: not set
Component: DRM/Intel
Assignee: intel-gfx-bugs at lists.freedesktop.org
Reporter: lakshminarayana.vudum at intel.com
QA Contact: intel-gfx-bugs at lists.freedesktop.org
CC: intel-gfx-bugs at lists.freedesktop.org
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7375/shard-tglb6/igt@i915_selftest@live_gt_mocs.html
<6> [60.377726] [IGT] i915_selftest: executing
<6> [60.382172] [IGT] i915_selftest: starting subtest live_gt_mocs
<5> [60.435098] Setting dangerous option live_selftests - tainting kernel
<6> [60.455852] [drm] i915.alpha_support is deprecated, use
i915.force_probe=9a49 instead
<7> [60.456204] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 2048K
<7> [60.456268] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]]
enable_guc=0 (guc:no submission:no huc:no)
<7> [60.456380] [drm:intel_pch_type [i915]] Found Tiger Lake LP PCH
<7> [60.456468] [drm:intel_power_domains_init [i915]] Allowed DC state mask
4000000a
<7> [60.457040] [drm:intel_device_info_init_mmio [i915]] vdbox enable: 0005,
instances: 0005
<7> [60.457083] [drm:intel_device_info_init_mmio [i915]] vebox enable: 0001,
instances: 0001
<7> [60.457263] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M
<7> [60.457388] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
<7> [60.457424] [drm:i915_ggtt_probe_hw [i915]] DSM size = 60M
<6> [60.457433] i915 0000:00:02.0: vgaarb: deactivate vga console
<7> [60.457725] [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED =
0x000000004f2000c7
<7> [60.457802] [drm:init_stolen [i915]] Memory reserved for graphics device:
61440K, usable: 59392K
<7> [60.458023] [drm:i915_driver_probe [i915]] Initialized 2 GT workarounds on
global
<7> [60.458176] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
<7> [60.458222] [drm:intel_opregion_setup [i915]] graphic opregion physical
addr: 0x44961018
<7> [60.458296] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.1.0
<7> [60.458380] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
<7> [60.458416] [drm:intel_opregion_setup [i915]] SWSCI supported
<7> [60.483448] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks
00000cb3, SBCB callbacks 00300583
<7> [60.483492] [drm:intel_opregion_setup [i915]] ASLE supported
<7> [60.483527] [drm:intel_opregion_setup [i915]] ASLE extension supported
<7> [60.483560] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI
OpRegion (Mailbox #4)
<7> [60.483594] [drm:i915_driver_probe [i915]] DRAM type: DDR4
<7> [60.483624] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 8 GB,
width: X8, ranks: 1, 16Gb DIMMs: no
<7> [60.483648] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB,
width: X0, ranks: 0, 16Gb DIMMs: no
<7> [60.483670] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 1, 16Gb
DIMMs: no
<7> [60.483693] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 0 GB,
width: X0, ranks: 0, 16Gb DIMMs: no
<7> [60.483714] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB,
width: X0, ranks: 0, 16Gb DIMMs: no
<7> [60.483735] [drm:skl_dram_get_channel_info [i915]] CH1 not populated
<7> [60.483755] [drm:i915_driver_probe [i915]] Memory configuration is
symmetric? no
<7> [60.483777] [drm:i915_driver_probe [i915]] DRAM bandwidth: 17066672 kBps,
channels: 1
<7> [60.483798] [drm:i915_driver_probe [i915]] DRAM ranks: 1, 16Gb DIMMs: no
<7> [60.483888] [drm:icl_get_bw_info [i915]] QGV 0: DCLK=128 tRP=15 tRDPRE=8
tRAS=35 tRCD=15 tRC=50
<7> [60.483925] [drm:icl_get_bw_info [i915]] BW0 / QGV 0: num_planes=2
deratedbw=14894
<7> [60.483959] [drm:icl_get_bw_info [i915]] BW1 / QGV 0: num_planes=1
deratedbw=20061
<7> [60.483994] [drm:intel_bios_init [i915]] Skipping VBT init due to disabled
display.
<7> [60.484255] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
<7> [60.484421] [drm:intel_power_domains_init_hw [i915]] rawclk rate: 19200 kHz
<7> [60.484463] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
<7> [60.484542] [drm:intel_combo_phy_init [i915]] Combo PHY A already enabled,
won't reprogram it.
<7> [60.484610] [drm:intel_combo_phy_init [i915]] Combo PHY B already enabled,
won't reprogram it.
<7> [60.484689] [drm:intel_power_well_enable [i915]] enabling power well 1
<7> [60.484770] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 172800 kHz,
VCO 345600 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<7> [60.484831] [drm:intel_power_well_enable [i915]] enabling always-on
<7> [60.484864] [drm:intel_power_well_enable [i915]] enabling DC off
<7> [60.484896] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
<7> [60.484982] [drm:intel_combo_phy_init [i915]] Combo PHY A already enabled,
won't reprogram it.
<7> [60.485035] [drm:intel_combo_phy_init [i915]] Combo PHY B already enabled,
won't reprogram it.
<7> [60.485069] [drm:intel_power_well_enable [i915]] enabling power well 2
<7> [60.485105] [drm:intel_power_well_enable [i915]] enabling power well 3
<7> [60.485167] [drm:intel_power_well_enable [i915]] enabling power well 4
<7> [60.485201] [drm:intel_power_well_enable [i915]] enabling power well 5
<7> [60.485360] [drm:intel_csr_ucode_init [i915]] Loading
i915/tgl_dmc_ver2_04.bin
<7> [60.487101] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
<7> [60.487152] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2
(2.0 usec)
<7> [60.487180] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 59
(59.0 usec)
<6> [60.487181] [drm] Finished loading DMC firmware i915/tgl_dmc_ver2_04.bin
(v2.4)
<7> [60.487206] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 68
(68.0 usec)
<7> [60.487228] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 72
(72.0 usec)
<7> [60.487251] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 103
(103.0 usec)
<7> [60.487273] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 117
(117.0 usec)
<7> [60.487354] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 123
(123.0 usec)
<7> [60.487376] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 139
(139.0 usec)
<7> [60.487421] [drm:intel_modeset_init [i915]] 4 display pipes available.
<7> [60.487493] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 172800 kHz,
VCO 345600 kHz, ref 38400 kHz, bypass 19200 kHz, voltage level 0
<6> [60.487589] mei_hdcp mei::b638ab7e-94e2-4ea2-a552-d1c54b627f04:01: bound
0000:00:02.0 (ops i915_hdcp_component_ops [i915])
<7> [60.487665] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 652800
kHz
<7> [60.487735] [drm:intel_modeset_init [i915]] Max dotclock rate: 1305600 kHz
<7> [60.488121] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488159] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488200] [drm:intel_modeset_setup_hw_state [i915]] TBT PLL hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488240] [drm:intel_modeset_setup_hw_state [i915]] TC PLL 1 hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488283] [drm:intel_modeset_setup_hw_state [i915]] TC PLL 2 hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488346] [drm:intel_modeset_setup_hw_state [i915]] TC PLL 3 hw state
readout: crtc_mask 0x00000000, on 0
<7> [60.488384] [drm:intel_modeset_setup_hw_state [i915]] TC PLL 4 hw state
readout: crtc_mask 0x00000000, on 0
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