[Bug 111562] [CI][BAT] igt at gem* - fail / dmesg-fail - Failed assertion: !"GPU hung"
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Fri Sep 6 17:21:40 UTC 2019
https://bugs.freedesktop.org/show_bug.cgi?id=111562
Chris Wilson <chris at chris-wilson.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #7 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit 5bf05dc58d65b215437df3013163a7eea78d5d4c (HEAD -> drm-intel-next-queued,
drm-intel/drm-intel-next-queued)
Author: Michel Thierry <michel.thierry at intel.com>
Date: Fri Sep 6 15:23:14 2019 +0300
drm/i915/tgl: Register state context definition for Gen12
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: alias, virtual engine, rpcs, prune unused regs
v3: use engine base (Daniele), take ctx_bb for all
Bspec: 46255
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: José Roberto de Souza <jose.souza at intel.com>
Signed-off-by: Michel Thierry <michel.thierry at intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Tested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
[ickle: Tweaked the GEM_WARN_ON after settling on a compromise with
Daniele]
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Link:
https://patchwork.freedesktop.org/patch/msgid/20190906122314.2146-2-mika.kuoppala@linux.intel.com
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