[Bug 111743] [CI][DRMTIP] igt at kms_psr@psr2_sprite_render - fail - Failed assertion: psr_wait_entry_if_enabled(data), PSR sink implementation is not reliable

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=111743

--- Comment #2 from Jose Roberto de Souza <jose.souza at intel.com> ---
A FIFO underrun caused a PSR CRC mismatch and after that we don't enable PSR
anymore to avoid further glitches.

<3>[  135.106379] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun
<7>[  135.106573] [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to
FIFO underrun.
<7>[  135.122201] [drm:gen8_de_irq_handler [i915]] hotplug event received, stat
0x00010000, dig 0x00000889, pins 0x00000010, long 0x00000000
<7>[  135.122247] [drm:intel_hpd_irq_handler [i915]] digital hpd on
[ENCODER:275:DDI A] - short
<7>[  135.122318] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on
[ENCODER:275:DDI A] - short
<7>[  135.123563] [drm:intel_dp_read_dpcd [i915]] Base DPCD: 14 0a 82 41 00 00
01 c0 02 00 00 00 0f 09 80
<7>[  135.123601] [drm:intel_dp_read_dpcd [i915]] DPCD: 14 0a 82 c1 00 00 01 c0
02 00 00 00 0f 09 80
<7>[  135.124530] [drm:intel_psr_enable_locked [i915]] Enabling PSR1
<7>[  135.125051] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<3>[  135.126007] [drm:intel_psr_short_pulse [i915]] *ERROR* PSR Link CRC
error, disabling PSR

We probably have issues open for the TGL FIFO underrruns, fixing those would
fix this one.

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