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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [byt] Bad powerwell for display reg read during interrupt handler (valleyview_pipestat_irq_handle)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93738#c1">Comment # 1</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [byt] Bad powerwell for display reg read during interrupt handler (valleyview_pipestat_irq_handle)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93738">bug 93738</a>
from <span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span></b>
<pre>Hmm. I wonder why were not getting this all the time. Or are we?
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1651,6 +1651,12 @@ static void valleyview_pipestat_irq_handler(struct
drm_device *dev, u32 iir)
int pipe;
spin_lock(&dev_priv->irq_lock);
+
+ if (!dev_priv->display_irqs_enabled) {
+ spin_unlock(&dev_priv->irq_lock);
+ return;
+ }
+
for_each_pipe(dev_priv, pipe) {
i915_reg_t reg;
u32 mask, iir_bit = 0;</pre>
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