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<body><span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span> changed
<a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Kernel DRM/i915 init sends eDP panel into self-test loop"
href="https://bugs.freedesktop.org/show_bug.cgi?id=94338">bug 94338</a>
<br>
<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Status</td>
<td>NEW
</td>
<td>NEEDINFO
</td>
</tr></table>
<p>
<div>
<b><a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Kernel DRM/i915 init sends eDP panel into self-test loop"
href="https://bugs.freedesktop.org/show_bug.cgi?id=94338#c8">Comment # 8</a>
on <a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Kernel DRM/i915 init sends eDP panel into self-test loop"
href="https://bugs.freedesktop.org/show_bug.cgi?id=94338">bug 94338</a>
from <span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span></b>
<pre>(In reply to infernix from <a href="show_bug.cgi?id=94338#c7">comment #7</a>)
<span class="quote">> Without "[PATCH] drm: Don't send i2c start via bare address packet" applied
> and on drm-intel-nightly, no result.
>
> Not sure what data you need but: dmesg|egrep -i
> 'panel|modeline|edid|vbt|dpcd'
>
>
> [ 5.567684] [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion
> (Mailbox #4)
> [ 5.568386] [drm:init_vbt_defaults] Set default to SSC at 120000 kHz
> [ 5.568388] [drm:intel_bios_init] VBT signature "$VBT SKYLAKE ",
> BDB version 196
> [ 5.568397] [drm:parse_lfp_panel_data] DRRS supported mode is static
> [ 5.568401] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT
> tables:
> [ 5.568405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 5.568407] [drm:parse_lfp_panel_data] VBT initial LVDS value 300
> [ 5.568410] [drm:parse_lfp_backlight] VBT backlight PWM modulation
> frequency 200 Hz, active high, min brightness 0, level 255
> [ 5.568419] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1
> CRT:0
> [ 5.568421] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0
> [ 5.568424] [drm:parse_ddi_port] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0
> CRT:0
> [ 5.568426] [drm:parse_ddi_port] VBT HDMI level shift for port B: 3
> [ 5.572174] [drm:intel_dp_init_panel_power_sequencer] cur t1_t3 0 t8 0 t9
> 0 t10 500 t11_t12 6000
> [ 5.572177] [drm:intel_dp_init_panel_power_sequencer] vbt t1_t3 2000 t8
> 10 t9 2000 t10 500 t11_t12 5000
> [ 5.572179] [drm:intel_dp_init_panel_power_sequencer] panel power up
> delay 200, power down delay 50, power cycle delay 600
> [ 5.572181] [drm:intel_dp_init_panel_power_sequencer] backlight on delay
> 1, off delay 200
> [ 5.572388] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [ 5.572441] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL:
> 0xabcd000f
> [ 5.573443] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 01 00 00 01 80 02 00
> 00 00 00 01 00
> [ 5.574314] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source
> yes, sink no
> [ 5.574385] [drm:intel_dp_init_panel_power_sequencer_registers] panel
> power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV
> 0x4af06
> [ 5.576066] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight
> initialized, enabled, brightness 937/937
> [ 5.576600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60
> 118654 1600 1624 1704 2112 900 901 904 934 0x40 0x9
> [ 5.576610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x900" 60
> 118654 1600 1624 1704 2112 900 901 904 934 0x40 0x9
> [ 5.576710] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0
> 0 0 0 0 0x0 0x0
> [ 5.576719] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0
> 0 0 0 0 0x0 0x0
> [ 5.583233] [drm:drm_mode_debug_printmodeline] Modeline 42:"1024x768" 60
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 5.708915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 5.708922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 5.911928] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
> [ 5.919041] [drm:edp_panel_off] Turn eDP port A panel power off
> [ 5.919065] [drm:wait_panel_off] Wait for panel power off time
> [ 5.919083] [drm:wait_panel_status] mask b0000000 value 00000000 status
> 80000008 control abcd0000
> [ 5.979779] [drm:wait_panel_status] Wait complete
> [ 5.979834] [drm:edp_panel_on] Turn eDP port A panel power on
> [ 5.979842] [drm:wait_panel_power_cycle] Wait for panel power cycle
> [ 6.523931] [drm:wait_panel_status] mask b800000f value 00000000 status
> 08000001 control abcd0000
> [ 6.564384] [drm:wait_panel_status] Wait complete
> [ 6.564410] [drm:wait_panel_on] Wait for panel power on
> [ 6.564427] [drm:wait_panel_status] mask b000000f value 80000008 status
> 0000000a control abcd0003
> [ 6.766666] [drm:wait_panel_status] Wait complete
> [ 6.766686] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [ 6.766734] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL:
> 0xabcd000b
> [ 6.772351] [drm:intel_panel_enable_backlight] pipe A
> [ 6.772389] [drm:intel_panel_actually_set_backlight] set backlight PWM =
> 937
> [ 6.772428] [drm:intel_psr_enable] PSR not supported by this panel
> [ 6.772428] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
> [ 6.792150] [drm:drm_mode_debug_printmodeline] Modeline 42:"1024x768" 60
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 9.799795] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [ 9.799844] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008
> PP_CONTROL: 0xabcd0007
> [ 12.297289] [drm:intel_panel_actually_set_backlight] set backlight PWM =
> 937
> [ 22.532755] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
> [ 22.532804] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL:
> 0xabcd000f
> [ 22.535912] [drm:drm_mode_debug_printmodeline] Modeline 42:"1024x768" 60
> 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
> [ 25.536183] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
> [ 25.536226] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008
> PP_CONTROL: 0xabcd0007</span >
Full dmesg please, I need to see the modeset to make sure it picked the right
mode.</pre>
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