<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - Endless loop in intel_power_well_enable "enabling always-on" / "disabling always-on" on DPMS off" href="https://bugs.freedesktop.org/show_bug.cgi?id=94422#c2">Comment # 2</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - Endless loop in intel_power_well_enable "enabling always-on" / "disabling always-on" on DPMS off" href="https://bugs.freedesktop.org/show_bug.cgi?id=94422">bug 94422</a> from <a class="email" href="mailto:tvrtko.ursulin@linux.intel.com" title="Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>"> Tvrtko Ursulin</a> <pre>On todays (07th March 2016.) behaviour is a bit different. It doesn't seem to get into the power well loop, but there are some wakeref asserts: [15044.919545] [drm:connected_sink_compute_bpp] [CONNECTOR:32:eDP-1] checking for sink bpp constrains [15044.929795] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [15044.940359] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [15044.952632] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [15044.963289] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [15044.972192] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [15044.981186] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880147eca000 for pipe A [15044.990958] [drm:intel_dump_pipe_config] cpu_transcoder: D [15044.997181] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [15045.004292] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [15045.015840] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [15045.029168] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [15045.040706] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [15045.047527] [drm:intel_dump_pipe_config] requested mode: [15045.053550] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [15045.066584] [drm:intel_dump_pipe_config] adjusted mode: [15045.072512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [15045.085630] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [15045.098471] [drm:intel_dump_pipe_config] port clock: 270000 [15045.104791] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [15045.111709] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [15045.120895] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [15045.132851] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [15045.142618] [drm:intel_dump_pipe_config] ips: 1 [15045.147768] [drm:intel_dump_pipe_config] double wide: 0 [15045.153694] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [15045.164165] [drm:intel_dump_pipe_config] planes on this crtc [15045.170585] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled [15045.179174] [drm:intel_dump_pipe_config] FB:55, fb = 1920x1080 format = 0x34325258[15045.187874] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080 [15045.197444] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 enabled [15045.205835] [drm:intel_dump_pipe_config] FB:49, fb = 64x64 format = 0x34325241[15045.214137] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 64x64 dst (959, 539) 64x64 [15045.223313] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0 [15045.233679] [drm:intel_modeset_checks] New cdclk calculated to be atomic 337500, actual 337500 [15045.243457] [drm:intel_power_well_enable] enabling display [15045.249678] [drm:hsw_set_power_well] Enabling power well [15045.262607] [drm:intel_edp_backlight_off] [15045.467668] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [15045.475480] [drm:intel_disable_pipe] disabling pipe A [15045.497860] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [15045.504316] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [15045.512753] [drm:edp_panel_off] Turn eDP port A panel power off [15045.519472] [drm:wait_panel_off] Wait for panel power off time [15045.526096] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control abcd0000 [15045.573593] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x00000012, pins 0x00000010 [15045.584843] [drm:intel_hpd_irq_handler] digital hpd port A - long [15045.591750] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [15045.600647] [drm:wait_panel_status] Wait complete [15045.600658] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [15045.613206] [drm:__intel_fbc_disable] Disabling FBC on pipe A [15045.619729] [drm:intel_power_well_disable] disabling always-on [15045.626346] [drm:intel_power_well_disable] disabling display [15045.632766] [drm:hsw_set_power_well] Requesting to disable the power well [15045.640467] [drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access [15045.649150] [drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access[drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access [15045.665243] [drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access[drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access [15045.681343] [drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access[drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access [15045.697437] [drm:assert_rpm_wakelock_held] RPM wakelock ref not held during HW access[15045.706334] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1] [15045.713338] [drm:intel_power_well_enable] enabling always-on [15045.719755] [drm:intel_power_well_disable] disabling always-on [15045.726368] [drm:check_encoder_state] [ENCODER:31:TMDS-31] [15045.732590] [drm:check_encoder_state] [ENCODER:40:TMDS-40] [15045.738823] [drm:intel_power_well_enable] enabling always-on [15045.745248] [drm:intel_power_well_disable] disabling always-on [15045.751871] [drm:check_encoder_state] [ENCODER:42:DP MST-42] [15045.758290] [drm:check_encoder_state] [ENCODER:43:DP MST-43] [15045.764710] [drm:check_encoder_state] [ENCODER:44:DP MST-44] [15045.771129] [drm:check_encoder_state] [ENCODER:47:TMDS-47] [15045.777359] [drm:intel_power_well_enable] enabling always-on [15045.783775] [drm:intel_power_well_disable] disabling always-on [15045.790389] [drm:check_crtc_state] [CRTC:21] [15045.795228] [drm:intel_power_well_enable] enabling always-on [15045.801647] [drm:intel_power_well_disable] disabling always-on [15045.808261] [drm:intel_power_well_enable] enabling always-on [15045.814682] [drm:intel_power_well_disable] disabling always-on [15045.821297] [drm:check_shared_dpll_state] WRPLL 1 [15045.826631] [drm:intel_power_well_enable] enabling always-on [15045.833053] [drm:intel_power_well_disable] disabling always-on [15045.839666] [drm:check_shared_dpll_state] WRPLL 2 [15045.844999] [drm:intel_power_well_enable] enabling always-on [15045.851416] [drm:intel_power_well_disable] disabling always-on [15045.858042] [drm:check_shared_dpll_state] SPLL [15045.863081] [drm:intel_power_well_enable] enabling always-on [15045.869501] [drm:intel_power_well_disable] disabling always-on <key press to wake up the screen> [16189.517098] [drm:drm_mode_setcrtc] [CRTC:21:crtc-0] [16189.522670] [drm:drm_mode_setcrtc] [CONNECTOR:32:eDP-1] [16189.528683] [drm:connected_sink_compute_bpp] [CONNECTOR:32:eDP-1] checking for sink bpp constrains [16189.538881] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24 [16189.549362] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz [16189.561624] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24 [16189.572276] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000 [16189.581159] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0 [16189.590145] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880147d5f800 for pipe A [16189.599916] [drm:intel_dump_pipe_config] cpu_transcoder: D [16189.599917] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [16189.599928] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [16189.599931] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64 [16189.599932] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0 [16189.599933] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [16189.599933] [drm:intel_dump_pipe_config] requested mode: [16189.599936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x0 0xa [16189.599936] [drm:intel_dump_pipe_config] adjusted mode: [16189.599938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa [16189.599940] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa [16189.599941] [drm:intel_dump_pipe_config] port clock: 270000 [16189.599942] [drm:intel_dump_pipe_config] pipe src size: 1920x1080 [16189.599942] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0 [16189.599944] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [16189.599945] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [16189.599945] [drm:intel_dump_pipe_config] ips: 1 [16189.599946] [drm:intel_dump_pipe_config] double wide: 0 [16189.599947] [drm:intel_dump_pipe_config] ddi_pll_sel: 0x20000000; dpll_hw_state: wrpll: 0x0 spll: 0x0 [16189.599948] [drm:intel_dump_pipe_config] planes on this crtc [16189.599951] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled [16189.599953] [drm:intel_dump_pipe_config] FB:55, fb = 1920x1080 format = 0x34325258 [16189.599953] [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 1920x1080 dst (0, 0) 1920x1080 [16189.599954] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0 [16189.599955] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0 [16189.599957] [drm:intel_modeset_checks] New cdclk calculated to be atomic 337500, actual 337500 [16189.599968] [drm:intel_power_well_enable] enabling display [16189.599970] [drm:hsw_set_power_well] Enabling power well [16189.601987] [drm:intel_power_well_enable] enabling always-on [16189.602015] [drm:edp_panel_on] Turn eDP port A panel power on [16189.602018] [drm:wait_panel_power_cycle] Wait for panel power cycle [16189.602022] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000 [16189.602024] [drm:wait_panel_status] Wait complete [16189.602030] [drm:wait_panel_on] Wait for panel power on [16189.602034] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003 [16189.713692] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x00000012, pins 0x00000010 [16189.713693] [drm:intel_hpd_irq_handler] digital hpd port A - long [16189.713693] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0 [16189.713715] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A [16189.822091] [drm:wait_panel_status] Wait complete [16189.822095] [drm:edp_panel_vdd_on] Turning eDP port A VDD on [16189.822104] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b [16189.843003] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [16189.843004] [drm:intel_dp_set_signal_levels] Using vswing level 0 [16189.843004] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [16189.861963] [drm:intel_dp_link_training_clock_recovery] clock recovery OK [16189.884490] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful [16189.884614] [drm:intel_enable_pipe] enabling pipe A [16189.890409] [drm:intel_edp_backlight_on] [16189.890412] [drm:intel_panel_enable_backlight] pipe A [16189.890423] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [16189.890444] [drm:intel_psr_enable] PSR not supported by this panel [16189.890444] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS [16189.890447] [drm:intel_fbc_alloc_cfb] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1 [16189.890447] [drm:intel_fbc_enable] Enabling FBC on pipe A [16189.920665] [drm:intel_power_well_disable] disabling display [16189.920672] [drm:hsw_set_power_well] Requesting to disable the power well [16189.920675] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1] [16189.920678] [drm:check_encoder_state] [ENCODER:31:TMDS-31] [16189.920679] [drm:check_encoder_state] [ENCODER:40:TMDS-40] [16189.920681] [drm:check_encoder_state] [ENCODER:42:DP MST-42] [16189.920681] [drm:check_encoder_state] [ENCODER:43:DP MST-43] [16189.920682] [drm:check_encoder_state] [ENCODER:44:DP MST-44] [16189.920682] [drm:check_encoder_state] [ENCODER:47:TMDS-47] [16189.920684] [drm:check_crtc_state] [CRTC:21] [16189.920703] [drm:check_shared_dpll_state] WRPLL 1 [16189.920704] [drm:check_shared_dpll_state] WRPLL 2 [16189.920706] [drm:check_shared_dpll_state] SPLL [16189.920727] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=937/937 [16189.920728] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [16192.896585] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [16192.903734] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> <li>You are the QA Contact for the bug.</li> <li>You are on the CC list for the bug.</li> </ul> </body> </html>