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<b><a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - [APL][Linux]: HDMI / DP are not responding properly in APL"
href="https://bugs.freedesktop.org/show_bug.cgi?id=94044#c12">Comment # 12</a>
on <a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - [APL][Linux]: HDMI / DP are not responding properly in APL"
href="https://bugs.freedesktop.org/show_bug.cgi?id=94044">bug 94044</a>
from <span class="vcard"><a class="email" href="mailto:jim.bride@linux.intel.com" title="Jim Bride <jim.bride@linux.intel.com>"> <span class="fn">Jim Bride</span></a>
</span></b>
<pre>There are several things that could be at play here. First off, since we're
looking at BXT-P A0, then DDI1 (Port C) cannot be used. If you're plugging
monitors in on that port, then the lack of a routed HPD signal to that port
will prevent hot plugs from working correctly. Secondly, until LSPCON gets
into the kernel DDI0 (Port B) is also not going to behave reliably. I strongly
recommend moving to B0 silicon for all external monitor testing, and even then
I wouldn't get super excited about it until the LSPCON patches land.
One other curious thing I saw:
Feb 11 08:36:51 apl kernel: [53111.664336] [drm:intel_dp_compute_config] DP
link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
Feb 11 08:36:51 apl kernel: [53111.664359] [drm:intel_dp_compute_config] DP
link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
Feb 11 08:36:51 apl kernel: [53111.664366] [drm:intel_dp_compute_config] DP
link bw required 333072 available 432000
Does the APL panel only support two lanes of DP? I'm also seeing that we're
only training at HBR1. Is CDCLK being set in the BIOS, and if so to what
value? On SKL+ the CDCLK setting has a direct bearing on how fast the ports
can run. In any event, please retest ensuring that CDCLK is set to maximum and
then let's see if at least eDP works without flickering in this scenario.</pre>
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