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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [IVB bisected] *ERROR* uncleared fifo underrun on pipe A"
href="https://bugs.freedesktop.org/show_bug.cgi?id=95736">95736</a>
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<th>Summary</th>
<td>[IVB bisected] *ERROR* uncleared fifo underrun on pipe A
</td>
</tr>
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<th>Product</th>
<td>DRI
</td>
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<th>Version</th>
<td>DRI git
</td>
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<th>Hardware</th>
<td>x86-64 (AMD64)
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>medium
</td>
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<th>Component</th>
<td>DRM/Intel
</td>
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<th>Assignee</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
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<th>Reporter</th>
<td>chris.bainbridge@gmail.com
</td>
</tr>
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<th>QA Contact</th>
<td>intel-gfx-bugs@lists.freedesktop.org
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<th>CC</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr></table>
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<pre>Looks similar to <a class="bz_bug_link
bz_status_NEW "
title="NEW - [IVB bisected] switching to tty1 causes fifo underrun on pipe B and pipe C"
href="show_bug.cgi?id=93802">bug #93802</a> but now occurs on pipe A every boot:
[ 1.446499] [drm:intel_set_cpu_fifo_underrun_reporting] *ERROR* uncleared
fifo underrun on pipe A
[ 1.446501] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A
FIFO underrun
[ 1.554896] [drm:intel_check_pch_fifo_underruns] *ERROR* pch fifo underrun
on pch transcoder A
Bisect result:
ed4a6a7ca853253f9b86f3005d76345482a71283 is the first bad commit
commit ed4a6a7ca853253f9b86f3005d76345482a71283
Author: Matt Roper <<a href="mailto:matthew.d.roper@intel.com">matthew.d.roper@intel.com</a>>
Date: Tue Feb 23 17:20:13 2016 -0800
drm/i915: Add two-stage ILK-style watermark programming (v11)</pre>
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