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<b><a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - [BSW] External HDMI monitor suddenly shows solid color when playing Youtube video at 1080p [fifo underrun]"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97965#c42">Comment # 42</a>
on <a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - [BSW] External HDMI monitor suddenly shows solid color when playing Youtube video at 1080p [fifo underrun]"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97965">bug 97965</a>
from <span class="vcard"><a class="email" href="mailto:ykku16dev2@gmail.com" title="Yu Kang Ku <ykku16dev2@gmail.com>"> <span class="fn">Yu Kang Ku</span></a>
</span></b>
<pre>(In reply to Ville Syrjala from <a href="show_bug.cgi?id=97965#c39">comment #39</a>)
<span class="quote">> (In reply to Yu Kang Ku from <a href="show_bug.cgi?id=97965#c38">comment #38</a>)
> > (In reply to Ville Syrjala from <a href="show_bug.cgi?id=97965#c37">comment #37</a>)
> > > Can we repeat the failure with, say, only pipe B active + DDR DVFS disabled
> > > + PM5 disabled + cxsr/maxfifo disabled + trickle feed enabled?</span >
I was finally able to simulate "closing the lid" on the BSW RVP and carry out
the experiment you requested. Unfortunately, the problem is still
reproducible.
The output of intel_watermark is here:
<a href="https://bugs.freedesktop.org/attachment.cgi?id=127636">https://bugs.freedesktop.org/attachment.cgi?id=127636</a>
The output of intel_reg dump --all is here:
<a href="https://bugs.freedesktop.org/attachment.cgi?id=127637">https://bugs.freedesktop.org/attachment.cgi?id=127637</a>
These outputs show that the conditions you specified have been met.
The following are the code changes I made to meet the conditions that you
specified:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d39ad2..35766b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -946,7 +946,7 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
- if (IS_CHERRYVIEW(dev_priv)) {
+ if (0 && IS_CHERRYVIEW(dev_priv)) {
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
@@ -1288,7 +1288,7 @@ static void vlv_merge_wm(struct drm_device *dev,
int num_active_crtcs = 0;
wm->level = to_i915(dev)->wm.max_level;
- wm->cxsr = true;
+ wm->cxsr = false;
for_each_intel_crtc(dev, crtc) {
const struct vlv_wm_state *wm_state = &crtc->wm_state;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168..10d6eac 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1070,7 +1070,7 @@ static void vlv_init_display_clock_gating(struct
drm_i915_private *dev_priv)
/*
* Disable trickle feed and enable pnd deadline calculation
*/
- I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+ I915_WRITE(MI_ARB_VLV, 0);
I915_WRITE(CBR1_VLV, 0);
WARN_ON(dev_priv->rawclk_freq == 0);</pre>
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