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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SKL] 5k tiled monitor DP sync issues"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97244#c19">Comment # 19</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [SKL] 5k tiled monitor DP sync issues"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97244">bug 97244</a>
from <span class="vcard"><a class="email" href="mailto:jani.nikula@intel.com" title="Jani Nikula <jani.nikula@intel.com>"> <span class="fn">Jani Nikula</span></a>
</span></b>
<pre>(In reply to Andrew Snow from <a href="show_bug.cgi?id=97244#c6">comment #6</a>)
<span class="quote">> Same problem here with Dell 5K and a Skylake i915 cpu/gpu.
>
> I think the problem is that the intel driver is assigning seperate PLLs for
> each port. The capability exists to share a common PLL clock source for
> both ports.
>
> I suspect the Windows driver sees both ports have the same resolution and
> framerate and shares a PLL automatically.</span >
If anyone does have the hardware and Windows readily available, dumping the PCI
MMIO BAR on Windows would let us check how it configures the hardware in this
case. Alas, I have no idea what the tool for dumping it is.</pre>
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