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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SNB][BAT] igt@gem_exec_flush@basic-batch-kernel-default-uc Failed assertion: intel_detect_and_clear_missed_interrupts(fd) == 0"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100007#c8">Comment # 8</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [SNB][BAT] igt@gem_exec_flush@basic-batch-kernel-default-uc Failed assertion: intel_detect_and_clear_missed_interrupts(fd) == 0"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100007">bug 100007</a>
from <span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span></b>
<pre> gen6_seqno_barrier(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ int loop;
/* Workaround to force correct ordering between irq and seqno writes on
* ivb (and maybe also on snb) by reading from a CS register (like
@@ -937,7 +938,8 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
* take the spinlock to guard against concurrent cacheline access.
*/
spin_lock_irq(&dev_priv->uncore.lock);
- POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
+ for (loop = 0; loop < 3; loop++)
+ POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
spin_unlock_irq(&dev_priv->uncore.lock);
was a bust.</pre>
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