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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - Enable UMD to control GPGPU EUs slice number in static/dynamic way"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100899#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - Enable UMD to control GPGPU EUs slice number in static/dynamic way"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100899">bug 100899</a>
from <span class="vcard"><a class="email" href="mailto:oscar.mateo@intel.com" title="Oscar Mateo <oscar.mateo@intel.com>"> <span class="fn">Oscar Mateo</span></a>
</span></b>
<pre>Hi Chris,
Userspace could adjust it via LRI, if only i915 whitelists GEN8_R_PWR_CLK_STATE
(this configuration from userspace via LRI is the preferred way for newer
platforms, and I was suggesting Dmitry the same thing could be done from BDW
onwards).</pre>
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