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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [IGT] [SKL/GLK/APL/BSW] kms_sysfs_edid_timing test assertion failure"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100047#c10">Comment # 10</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [IGT] [SKL/GLK/APL/BSW] kms_sysfs_edid_timing test assertion failure"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100047">bug 100047</a>
from <span class="vcard"><a class="email" href="mailto:clinton.a.taylor@intel.com" title="Clinton Taylor <clinton.a.taylor@intel.com>"> <span class="fn">Clinton Taylor</span></a>
</span></b>
<pre><a href="show_bug.cgi?id=100047#c8">comment #8</a> should read 1ms between 8 byte reads as seen in the scope shot
attached.
DDC operates at 100 Khz clock rate and AUX at 1 Mhz. eDP also only reads 128
bytes total compared to HDMI/DP reads of 256 or 512 bytes.
Are we sure 50ms is a valid test for DDC traffic?</pre>
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