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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [BAT][BYT,BSW] WARN_ON(dev_priv->uncore.funcs.mmio_readl(dev_priv, (((const i915_reg_t){ .reg = (0x180000 + 0x650C) })), true) & (1 << 27))"
href="https://bugs.freedesktop.org/show_bug.cgi?id=101517#c5">Comment # 5</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [BAT][BYT,BSW] WARN_ON(dev_priv->uncore.funcs.mmio_readl(dev_priv, (((const i915_reg_t){ .reg = (0x180000 + 0x650C) })), true) & (1 << 27))"
href="https://bugs.freedesktop.org/show_bug.cgi?id=101517">bug 101517</a>
from <span class="vcard"><a class="email" href="mailto:martin.peres@free.fr" title="Martin Peres <martin.peres@free.fr>"> <span class="fn">Martin Peres</span></a>
</span></b>
<pre>(In reply to Ville Syrjala from <a href="show_bug.cgi?id=101517#c4">comment #4</a>)
<span class="quote">> (In reply to krisman from <a href="show_bug.cgi?id=101517#c3">comment #3</a>)
> > (In reply to Martin Peres from <a href="show_bug.cgi?id=101517#c0">comment #0</a>)
> > > Starting from CI_DRM_2743, executing the tests
> > > igt@kms_pipe_crc_basic@suspend-read-crc-pipe-[ac] on our baytrails and
> > > braswells may lead to the following WARNING:
> > >
> > > [ 579.071526] [drm:chv_set_cdclk [i915]] *ERROR* timed out waiting for
> > > CDclk change
> > > [ 579.071942] WARN_ON(dev_priv->uncore.funcs.mmio_readl(dev_priv, (((const
> >
> > In the code, this WARN_ON carries the following comment:
> >
> > /*
> > * FIXME is this guaranteed to clear
> > * immediately or should we poll for it?
> > */
> > WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
> >
> > Maybe we should consider polling? :-)
> >
> > Anyway, that WARN_ON can be a side effect of the *ERROR* right before it.
> > I'm Looking into that. Also, I don't see much change in the commit log
> > between CI_DRM_2742 and CI_DRM_2743 that would explain it, but I will take a
> > deeper look.
>
> The simple solution would be to just revert commit 63ff30442519 ("drm/i915:
> Nuke the VLV/CHV PFI programming power domain workaround")
>
> I failed to consider that the firmware likes to reset the cdclk to some
> non-minimum frequency during suspend, and then we apparently perform a
> modeset without actually modesetting anything and thus only end up
> reprogramming the cdclk without the power well being enabled.</span >
Let's do it then! Revert fast, rework carefully.</pre>
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