<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEEDINFO " title="NEEDINFO - [BAT][SKL] *ERROR* failed to enable link training" href="https://bugs.freedesktop.org/show_bug.cgi?id=101144#c63">Comment # 63</a> on <a class="bz_bug_link bz_status_NEEDINFO " title="NEEDINFO - [BAT][SKL] *ERROR* failed to enable link training" href="https://bugs.freedesktop.org/show_bug.cgi?id=101144">bug 101144</a> from <a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> Ville Syrjala</a> <pre>Couple of observations I made: [ 5.001356] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000 [ 5.001412] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 2000 t9 2000 t10 500 t11_t12 5000 So the BIOS doesn't program the t1+t3 delay at all. Not sure why. The VBT seems to have these pps delays for most of the panel indexes: Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000 except panel 7 (which is what we end up using: Power Sequence: T3 2000 T7 2000 T9 2000 T10 500 T12 5000 So only T7 is changed, which shouldn't matter anyway. The panel spec would appear to list the following requirements: T1 0.5-10 ms T2/T3 0-200 ms T11 <= 10ms T12 >= 120 ms So it looks like the values we use should be fine in theory.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are on the CC list for the bug.</li> </ul> </body> </html>