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<b><a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED - [IGT] [SKL/GLK/APL/BSW/IVB/KBL/HSW /BYT] kms_sysfs_edid_timing test assertion failure"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100047#c18">Comment # 18</a>
on <a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED - [IGT] [SKL/GLK/APL/BSW/IVB/KBL/HSW /BYT] kms_sysfs_edid_timing test assertion failure"
href="https://bugs.freedesktop.org/show_bug.cgi?id=100047">bug 100047</a>
from <span class="vcard"><a class="email" href="mailto:marta.lofstedt@intel.com" title="Marta Löfstedt <marta.lofstedt@intel.com>"> <span class="fn">Marta Löfstedt</span></a>
</span></b>
<pre>(In reply to Clinton Taylor from <a href="show_bug.cgi?id=100047#c10">comment #10</a>)
<span class="quote">> <a href="show_bug.cgi?id=100047#c8">comment #8</a> should read 1ms between 8 byte reads as seen in the scope shot
> attached.
>
> DDC operates at 100 Khz clock rate and AUX at 1 Mhz. eDP also only reads 128
> bytes total compared to HDMI/DP reads of 256 or 512 bytes.
>
> Are we sure 50ms is a valid test for DDC traffic?</span >
Clinton, I tested OK with 100ms instead of 50ms on BDW/HDMI, since this was
based on your reasoning, could you send up an patch fixing the test.</pre>
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