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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI] igt@kms_atomic_transition@plane-all-modeset-[transition|transition-fencing] - Softdog incomplete"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103334#c11">Comment # 11</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI] igt@kms_atomic_transition@plane-all-modeset-[transition|transition-fencing] - Softdog incomplete"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103334">bug 103334</a>
from <span class="vcard"><a class="email" href="mailto:imre.deak@intel.com" title="Imre Deak <imre.deak@intel.com>"> <span class="fn">Imre Deak</span></a>
</span></b>
<pre>The reason for modesets taking long:
[ 34.061132] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500
t11_t12 6000
[ 34.061181] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000
t10 500 t11_t12 6000
[ 34.061220] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up
delay 200, power down delay 50, power cycle delay 600
[ 34.061259] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on
delay 1, off delay 200
So each modeset incurs all the above delays ~1050ms. I think the test should
set the number of iterations taking into account the above.</pre>
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