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<b><a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - [drm:intel_enable_lvds [i915]] *ERROR* timed out waiting for panel to power on"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103414#c7">Comment # 7</a>
on <a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - [drm:intel_enable_lvds [i915]] *ERROR* timed out waiting for panel to power on"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103414">bug 103414</a>
from <span class="vcard"><a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> <span class="fn">Ville Syrjala</span></a>
</span></b>
<pre>[ 14.589827] [drm:intel_lvds_init [i915]] LVDS PPS:t1+t2 500 t3 1 t4 10000 t5
2100 tx 50 divider 6249 port 0 powerdown_on_reset 1
So we have a power cycle delay of 1000 ms and power up delay of 5 ms. I guess
that explains why the timeout of 1000 ms isn't quite sufficient always.
We don't actually use the VBT PPS values on LVDS, but seeing the VBT would
still be interesting. So please do attach it.
Looking at the docs, the max power cycle delay we can program is 3 seconds and
the max power up delay is ~800 ms. Given those we should perhaps bump the
timeout to >=4 seconds. We seem to be using 5 seconds in the DP code, so I
think we might as well use that same value in the LVDS code.</pre>
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