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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI] igt@perf_pmu@multi-client-vecs0 - fail - Failed assertion: (double)(val[1]) <= (1.0 + (tolerance)) * (double)(slept) && (double)(val[1]) >= (1.0 - (tolerance)) * (double)(slept)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103886">103886</a>
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<th>Summary</th>
<td>[CI] igt@perf_pmu@multi-client-vecs0 - fail - Failed assertion: (double)(val[1]) <= (1.0 + (tolerance)) * (double)(slept) && (double)(val[1]) >= (1.0 - (tolerance)) * (double)(slept)
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<th>Product</th>
<td>DRI
</td>
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<th>Version</th>
<td>DRI git
</td>
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<th>Hardware</th>
<td>Other
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>medium
</td>
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<th>Component</th>
<td>DRM/Intel
</td>
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<th>Assignee</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr>
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<th>Reporter</th>
<td>marta.lofstedt@intel.com
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<th>QA Contact</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
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<th>CC</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr></table>
<p>
<div>
<pre><a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3377/shard-glkb6/igt@perf_pmu@multi-client-vecs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3377/shard-glkb6/igt@perf_pmu@multi-client-vecs0.html</a>
(perf_pmu:4132) CRITICAL: Test assertion failure function multi_client, file
perf_pmu.c:650:
(perf_pmu:4132) CRITICAL: Failed assertion: (double)(val[1]) <= (1.0 +
(tolerance)) * (double)(slept) && (double)(val[1]) >= (1.0 - (tolerance)) *
(double)(slept)
(perf_pmu:4132) CRITICAL: 'val[1]' != 'slept' (190889525.000000 not within
5.000000% tolerance of 166780280.000000)
Subtest multi-client-vecs0 failed.
Note this was previously filed on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI] igt@perf_pmu@* - fail - Failed assertion: (double)(val[i]) <= (1.0 + tolerance) * (double)0.0f && (double)(val[i]) >= (1.0 - tolerance) * (double)0.0f"
href="show_bug.cgi?id=103857">bug 103857</a>. However, that bug was fixed for a
lot of other tests and machines.</pre>
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