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<body><span class="vcard"><a class="email" href="mailto:bugs@mblankhorst.nl" title="Maarten Lankhorst <bugs@mblankhorst.nl>"> <span class="fn">Maarten Lankhorst</span></a>
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<a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Delay in skl_disable_plane() causes a system freeze"
href="https://bugs.freedesktop.org/show_bug.cgi?id=104975">bug 104975</a>
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<th>What</th>
<th>Removed</th>
<th>Added</th>
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<td style="text-align:right;">Status</td>
<td>NEW
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<td>NEEDINFO
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<b><a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Delay in skl_disable_plane() causes a system freeze"
href="https://bugs.freedesktop.org/show_bug.cgi?id=104975#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEEDINFO "
title="NEEDINFO - Delay in skl_disable_plane() causes a system freeze"
href="https://bugs.freedesktop.org/show_bug.cgi?id=104975">bug 104975</a>
from <span class="vcard"><a class="email" href="mailto:bugs@mblankhorst.nl" title="Maarten Lankhorst <bugs@mblankhorst.nl>"> <span class="fn">Maarten Lankhorst</span></a>
</span></b>
<pre>Hey,
I fear this is working as intended. With this information I can't narrow down
what is your real problem. :(
The relevant error here is:
[ 403.443634] [drm:drm_atomic_nonblocking_commit] committing 000000007afed85b
nonblocking
[ 403.544735] [drm:intel_cpu_fifo_underrun_irq_handler] *ERROR* CPU pipe A
FIFO underrun
[ 403.544750] [drm:intel_pipe_update_end] *ERROR* Atomic update failure on
pipe A (start=24896 end=24902) time 100023 us, min 1073, max 1079, scanline
start 450, end 457
[ 403.544762] [drm:intel_fbc_underrun_work_fn] Disabling FBC due to FIFO
underrun.
as can be seen in the dmesg, you get a lot of those ERRORs like below:
[ 403.544750] [drm:intel_pipe_update_end] *ERROR* Atomic update failure on
pipe A (start=24896 end=24902) time 100023 us, min 1073, max 1079, scanline
start 450, end 457
All of the code between pipe_update_start and pipe_update_end needs to run
without encountering a single vblank interrupt. As you can see in the dmesg,
hitting a vblank interrupt
results in this ERROR, and might cause FIFO underruns and even system hangs
because all the registers need to be updated in a single vblank interval.
Because of this pipe_update_start disables all local irqs and schedules the
update to be run at least 100 us away from the vblank interrupt, and
pipe_update_end complains loudly if we took longer than 100 us.
There's some code below in a ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE, you can
use it to report when a delay happened, without necessarily hitting any hang,
FIFO underrun or display corruption.
This might help you narrow down why vblank evasion sometimes takes longer than
100 us, or increase VBLANK_EVASION_TIME_US if necessary..
Good luck!</pre>
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