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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI] igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a - dmesg-warn - *ERROR* timeout during PHY0 power on"
href="https://bugs.freedesktop.org/show_bug.cgi?id=105771#c1">Comment # 1</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI] igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a - dmesg-warn - *ERROR* timeout during PHY0 power on"
href="https://bugs.freedesktop.org/show_bug.cgi?id=105771">bug 105771</a>
from <span class="vcard"><a class="email" href="mailto:imre.deak@intel.com" title="Imre Deak <imre.deak@intel.com>"> <span class="fn">Imre Deak</span></a>
</span></b>
<pre>After the timeout things seem to work correctly, the same PHY enabling will
succeed afterwards. Since the timeout isn't actually specified by BSpec, we
should just try increasing it:
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index c8e9e44e5981..00b3ab656b06 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private
*dev_priv,
* all 1s. Eventually they become accessible as they power up, then
* the reserved bit will give the default 0. Poll on the reserved bit
* becoming 0 to find when the PHY is accessible.
- * HW team confirmed that the time to reach phypowergood status is
- * anywhere between 50 us and 100us.
+ * The flag should get set in 100us according to the HW team, but
+ * use 1ms due to occasional timeouts observed with that.
*/
- if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
- (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
+ if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+ PHY_RESERVED | PHY_POWER_GOOD,
+ PHY_POWER_GOOD,
+ 1))
DRM_ERROR("timeout during PHY%d power on\n", phy);
- }
/* Program PLL Rcomp code offset */
val = I915_READ(BXT_PORT_CL1CM_DW9(phy));</pre>
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