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<body><span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][GDG] igt@drv_selftest@live_coherency igt_gem_coherency failed with error -22"
href="https://bugs.freedesktop.org/show_bug.cgi?id=107164">bug 107164</a>
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<th>What</th>
<th>Removed</th>
<th>Added</th>
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<td style="text-align:right;">Status</td>
<td>REOPENED
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<td>RESOLVED
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<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][GDG] igt@drv_selftest@live_coherency igt_gem_coherency failed with error -22"
href="https://bugs.freedesktop.org/show_bug.cgi?id=107164#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][GDG] igt@drv_selftest@live_coherency igt_gem_coherency failed with error -22"
href="https://bugs.freedesktop.org/show_bug.cgi?id=107164">bug 107164</a>
from <span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span></b>
<pre>Back for another soak.
commit a8bd3b884dd79dcc9a89dedd0e24b7554de4fe79 (HEAD -> drm-intel-next-queued,
drm-intel/for-linux-next, drm-intel/drm-intel-next-queued)
Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
Date: Tue Jul 17 10:26:55 2018 +0100
drm/i915: Flush chipset caches after GGTT writes
Our I915g (early gen3, the oldest machine we have in the farm) is still
reporting occasional incoherency performing the following operations:
1) write through GGTT (indirect write into memory)
2) write through either CPU or WC (direct write into memory)
3) read from GGTT (indirect read)
Instead of reporting the value from (2), the read from GGTT reports the
earlier value written via the GGTT. We have made sure that the writes are
flushed from the CPU (commit 3a32497f0dbe ("drm/i915/selftests: Provide
full mb() around clflush") and commit add00e6d896f ("drm/i915: Flush the
WCB following a WC write")), but still see the error, just less
frequently. The only remaining cache that might be affected here is a
chipset cache, so flush that as well.
Testcase: igt/drv_selftest/live_coherency #gdg
Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
Reviewed-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@intel.com">rodrigo.vivi@intel.com</a>>
Link:
<a href="https://patchwork.freedesktop.org/patch/msgid/20180717092655.28417-1-chris@chris-wilson.co.uk">https://patchwork.freedesktop.org/patch/msgid/20180717092655.28417-1-chris@chris-wilson.co.uk</a></pre>
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