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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][BAT] igt@*(s3|suspend|s4|hibernate)* - dmesg-warn - *ERROR* power well DC off state mismatch (refcount 0/enabled 1)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=107382#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][BAT] igt@*(s3|suspend|s4|hibernate)* - dmesg-warn - *ERROR* power well DC off state mismatch (refcount 0/enabled 1)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=107382">bug 107382</a>
from <span class="vcard"><a class="email" href="mailto:imre.deak@intel.com" title="Imre Deak <imre.deak@intel.com>"> <span class="fn">Imre Deak</span></a>
</span></b>
<pre>(In reply to Chris Wilson from <a href="show_bug.cgi?id=107382#c3">comment #3</a>)
<span class="quote">> I was having fun with powerwells accessing HAS_CSR before dev_info was set.</span >
Ok, AFAICS the issue here could result only from intel_dp_get/put which
shouldn't happen until after intel_power_domains_init_hw(). Checking now if
.has_csr=1 fixes it.</pre>
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