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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][BAT] igt@gem_sync@basic-many-each - fail - Failed assertion: !"GPU hung""
href="https://bugs.freedesktop.org/show_bug.cgi?id=107715#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][BAT] igt@gem_sync@basic-many-each - fail - Failed assertion: !"GPU hung""
href="https://bugs.freedesktop.org/show_bug.cgi?id=107715">bug 107715</a>
from <span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span></b>
<pre>ARGH. The answer is I never pushed
drm/i915/ringbuffer: Delay after invalidating gen6+ xcs
During stress testing of full-ppgtt (on Baytrail at least), we found
that the invalidation around a context/mm switch was insufficient (writes
would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but
it is unclear as to whether this is merely a delaying tactic or if it is
truly serialising with the TLB invalidation. Either way, it is
empirically required.
Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
Cc: Joonas Lahtinen <<a href="mailto:joonas.lahtinen@linux.intel.com">joonas.lahtinen@linux.intel.com</a>>
Cc: Mika Kuoppala <<a href="mailto:mika.kuoppala@linux.intel.com">mika.kuoppala@linux.intel.com</a>>
Cc: Matthew Auld <<a href="mailto:matthew.william.auld@gmail.com">matthew.william.auld@gmail.com</a>>
Cc: Tvrtko Ursulin <<a href="mailto:tvrtko.ursulin@intel.com">tvrtko.ursulin@intel.com</a>></pre>
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