<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [CI][BAT] igt@* - dmesg-warn - *ERROR* Panel status timeout" href="https://bugs.freedesktop.org/show_bug.cgi?id=108788#c2">Comment # 2</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [CI][BAT] igt@* - dmesg-warn - *ERROR* Panel status timeout" href="https://bugs.freedesktop.org/show_bug.cgi?id=108788">bug 108788</a> from <a class="email" href="mailto:ville.syrjala@linux.intel.com" title="Ville Syrjala <ville.syrjala@linux.intel.com>"> Ville Syrjala</a> <pre>The power sequencer delays are as follows: > <7> [310.447602] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600 > <7> [310.447694] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200 > <7> [310.447792] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x47d00001, PP_OFF 0x1f40001, PP_DIV 0x186906 (In reply to Martin Peres from <a href="show_bug.cgi?id=108788#c0">comment #0</a>) > The tests igt@drv_selftest@live_sanitycheck, igt@drv_module_reload@*, hit > this issue on ILK: > > <7> [311.456003] [drm:edp_panel_on [i915]] Turn eDP port A panel power on > <7> [311.456068] [drm:wait_panel_power_cycle [i915]] Wait for panel power > cycle > <7> [311.456213] [drm:wait_panel_status [i915]] mask b800000f value 00000000 > status 00000000 control abcd0008 > <7> [311.456310] [drm:wait_panel_status [i915]] Wait complete Panel is now in S0.0, power cycle delay not active. > <7> [311.456397] [drm:edp_panel_on [i915]] Wait for panel power on > <7> [311.456488] [drm:wait_panel_status [i915]] mask b000000f value 80000008 > status 9000000a control abcd0009 We just turned on the panel, and it has immediately reached S1.2. > <7> [311.531334] [drm:asle_work [i915]] bclp = 0x800000ea > <3> [316.458093] [drm:wait_panel_status [i915]] *ERROR* Panel status > timeout: status 90000009 control abcd0009 > <7> [316.458245] [drm:wait_panel_status [i915]] Wait complete Timeout after five seconds and the panel has only reached S1.1. Based on the earlier information T1+T2 was 200 ms, so we should have reached this state long ago. And the T5 delay is only 100 usec so we should reach S1.0 real soon now. > <7> [316.458851] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x90000009 PP_CONTROL: 0xabcd000b 600 usec elapsed, and we're still in S1.1. So feels like the state machine is making progress, but much slower than expected. PP_DIV 0x186906 is consistent with the rawclk readout > <7> [310.440356] [drm:i915_driver_load [i915]] rawclk rate: 125000 kHz This all looks rather strange. Maybe some clock gating w/a getting applied too late?</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> <li>You are the assignee for the bug.</li> <li>You are on the CC list for the bug.</li> </ul> </body> </html>