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    <body><span class="vcard"><a class="email" href="mailto:martin.peres@free.fr" title="Martin Peres <martin.peres@free.fr>"> <span class="fn">Martin Peres</span></a>
</span> changed
          <a class="bz_bug_link 
          bz_status_CLOSED  bz_closed"
   title="CLOSED FIXED - [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=108591">bug 108591</a>
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            <th>What</th>
            <th>Removed</th>
            <th>Added</th>
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         <tr>
           <td style="text-align:right;">Status</td>
           <td>RESOLVED
           </td>
           <td>CLOSED
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        <div>
            <b><a class="bz_bug_link 
          bz_status_CLOSED  bz_closed"
   title="CLOSED FIXED - [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=108591#c11">Comment # 11</a>
              on <a class="bz_bug_link 
          bz_status_CLOSED  bz_closed"
   title="CLOSED FIXED - [CI][DRMTIP] igt@gem_tiled_fence_blits@normal - fail - Failed assertion: linear[i] == start_val"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=108591">bug 108591</a>
              from <span class="vcard"><a class="email" href="mailto:martin.peres@free.fr" title="Martin Peres <martin.peres@free.fr>"> <span class="fn">Martin Peres</span></a>
</span></b>
        <pre>(In reply to Chris Wilson from <a href="show_bug.cgi?id=108591#c10">comment #10</a>)
<span class="quote">> commit 7fa28e146994da1e8a4124623d7da97b798ea520 (HEAD ->
> drm-intel-next-queued, drm-intel/for-linux-next,
> drm-intel/drm-intel-next-queued)
> Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
> Date:   Mon Nov 19 15:41:53 2018 +0000

>     drm/i915: Write GPU relocs harder with gen3
>     
>     Under moderate amounts of GPU stress, we can observe on Bearlake and
>     Pineview (later gen3 models) that we execute the following batch buffer
>     before the write into the batch is coherent. Adding extra (tested with
>     upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
>     not solve the incoherency issue with the relocations, but emitting the
>     MI_STORE_DWORD_IMM twice does. So be it.
>     
>     Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
>     Testcase: igt/gem_tiled_fence_blits # blb/pnv
>     Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
>     Cc: Joonas Lahtinen <<a href="mailto:joonas.lahtinen@linux.intel.com">joonas.lahtinen@linux.intel.com</a>>
>     Reviewed-by: Joonas Lahtinen <<a href="mailto:joonas.lahtinen@linux.intel.com">joonas.lahtinen@linux.intel.com</a>>
>     Link:
> <a href="https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1">https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1</a>-
> <a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a></span >

Oddly-enough, this was not sufficient to fix the issue, but it stopped failing
after drmtip_176
(<a href="https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_176/fi-gdg-551/igt@gem_tiled_fence_blits@normal.html">https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_176/fi-gdg-551/igt@gem_tiled_fence_blits@normal.html</a>),
so closing!</pre>
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