<html>
<head>
<base href="https://bugs.freedesktop.org/">
</head>
<body><span class="vcard"><a class="email" href="mailto:lakshminarayana.vudum@intel.com" title="Lakshmi <lakshminarayana.vudum@intel.com>"> <span class="fn">Lakshmi</span></a>
</span> changed
<a class="bz_bug_link
bz_status_NEW "
title="NEW - Kernel commit 7769db5883841b03de544a35a71ff528d4131c17 causes a Dell precision 5530 to no longer display a TTY"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110193">bug 110193</a>
<br>
<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Whiteboard</td>
<td>Triaged
</td>
<td>Triaged, ReadyForDev
</td>
</tr>
<tr>
<td style="text-align:right;">i915 features</td>
<td>
</td>
<td>display/Other
</td>
</tr>
<tr>
<td style="text-align:right;">Priority</td>
<td>medium
</td>
<td>high
</td>
</tr>
<tr>
<td style="text-align:right;">CC</td>
<td>
</td>
<td>james.ausmus@gmail.com, manasi.d.navare@intel.com
</td>
</tr>
<tr>
<td style="text-align:right;">Status</td>
<td>NEEDINFO
</td>
<td>NEW
</td>
</tr>
<tr>
<td style="text-align:right;">i915 platform</td>
<td>
</td>
<td>CFL
</td>
</tr></table>
<p>
<div>
<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - Kernel commit 7769db5883841b03de544a35a71ff528d4131c17 causes a Dell precision 5530 to no longer display a TTY"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110193#c3">Comment # 3</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - Kernel commit 7769db5883841b03de544a35a71ff528d4131c17 causes a Dell precision 5530 to no longer display a TTY"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110193">bug 110193</a>
from <span class="vcard"><a class="email" href="mailto:lakshminarayana.vudum@intel.com" title="Lakshmi <lakshminarayana.vudum@intel.com>"> <span class="fn">Lakshmi</span></a>
</span></b>
<pre>@Manasi can you help here?
[drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
[ 4.359796] [drm:intel_dp_start_link_train [i915]] Using LINK_RATE_SET value
05
[ 4.360291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels
00000000
[ 4.360313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
[ 4.360335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level
0
[ 4.360356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP
training pattern TPS1
[ 4.360983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels
00000000
[ 4.361004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
[ 4.361024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level
0
[ 4.361641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels
04000000
[ 4.361662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
[ 4.361683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level
0
[ 4.362299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels
07000000
[ 4.362319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
[ 4.362339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level
0
[ 4.362959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels
09000000
[ 4.362979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 3
[ 4.362999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level
0
[ 4.363616] [drm:intel_dp_start_link_train [i915]] Max Voltage Swing reached
[ 4.363637] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:85:eDP-1] Link
Training failed at link rate = 432000, lane count = 1
[ 4.363661] [drm:intel_dp_modeset_retry_work_fn [i915]] [CONNECTOR:85:eDP-1]
[ 4.364035] [drm:intel_enable_pipe [i915]] enabling pipe A
[ 4.364063] [drm:intel_edp_backlight_on [i915]]
[ 4.364086] [drm:intel_panel_enable_backlight [i915]] pipe A
[ 4.364134] [drm:intel_panel_actually_set_backlight [i915]] set backlight
PWM = 120000
[ 4.364255] [drm:intel_psr_enable_locked [i915]] Enabling PSR1
[ 4.364586] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
[ 4.365463] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of
contiguous stolen space for FBC, threshold: 1
[ 4.365487] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
[ 4.380828] [drm:verify_connector_state.isra.113 [i915]]
[CONNECTOR:85:eDP-1]
[ 4.380858] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe A]
[ 4.380891] [drm:verify_single_dpll_state.isra.146 [i915]] DPLL 0
[ 4.380916] [drm:intel_enable_sagv [i915]] Enabling SAGV
[ 4.380936] Console: switching to colour frame buffer device 240x67
[ 4.380955] [drm:drm_atomic_state_init [drm]] Allocated atomic state
00000000ae0f8d0f
[ 4.380964] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:30:plane 1A]
0000000028897fb8 state to 00000000ae0f8d0f
[ 4.380973] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe A]
000000001de39b56 state to 00000000ae0f8d0f
[ 4.380981] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:37:plane 2A]
0000000057c75e4e state to 00000000ae0f8d0f
[ 4.380988] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:37:plane 2A] state 0000000057c75e4e
[ 4.380996] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor A]
000000000eb53e82 state to 00000000ae0f8d0f
[ 4.381025] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:44:cursor A] state 000000000eb53e82
[ 4.381059] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state
00000000557ef946
[ 4.381070] [drm:__drm_atomic_state_free [drm]] Freeing atomic state
00000000557ef946
[ 4.381079] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:48:plane 1B]
00000000f063b462 state to 00000000ae0f8d0f
[ 4.381086] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:55:plane 2B]
00000000833163ae state to 00000000ae0f8d0f
[ 4.381092] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:55:plane 2B] state 00000000833163ae
[ 4.381100] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:62:cursor B]
000000008803fe15 state to 00000000ae0f8d0f
[ 4.381106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:62:cursor B] state 000000008803fe15
[ 4.381113] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:66:plane 1C]
00000000a81da555 state to 00000000ae0f8d0f
[ 4.381121] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 2C]
000000009a91f6d0 state to 00000000ae0f8d0f
[ 4.381127] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:73:plane 2C] state 000000009a91f6d0
[ 4.381134] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:80:cursor C]
000000001120099d state to 00000000ae0f8d0f
[ 4.381140] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:80:cursor C] state 000000001120099d
[ 4.381146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for
[PLANE:30:plane 1A] state 0000000028897fb8
[ 4.381154] [drm:drm_atomic_add_affected_connectors [drm]] Adding all
current connectors for [CRTC:47:pipe A] to 00000000ae0f8d0f
[ 4.381162] [drm:drm_atomic_get_connector_state [drm]] Added
[CONNECTOR:85:eDP-1] 00000000c1f7e681 state to 00000000ae0f8d0f
[ 4.381168] [drm:drm_atomic_set_crtc_for_connector [drm]] Link
[CONNECTOR:85:eDP-1] state 00000000c1f7e681 to [NOCRTC]
[ 4.381174] [drm:drm_atomic_set_crtc_for_connector [drm]] Link
[CONNECTOR:85:eDP-1] state 00000000c1f7e681 to [CRTC:47:pipe A]
[ 4.381182] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:65:pipe B]
00000000557ef946 state to 00000000ae0f8d0f
[ 4.381188] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for
[CRTC:65:pipe B] state 00000000557ef946
[ 4.381193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:48:plane 1B] state 00000000f063b462
[ 4.381201] [drm:drm_atomic_add_affected_connectors [drm]] Adding all
current connectors for [CRTC:65:pipe B] to 00000000ae0f8d0f
[ 4.381209] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:83:pipe C]
00000000d98f8725 state to 00000000ae0f8d0f
[ 4.381214] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for
[CRTC:83:pipe C] state 00000000d98f8725
[ 4.381220] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for
[PLANE:66:plane 1C] state 00000000a81da555
[ 4.381227] [drm:drm_atomic_add_affected_connectors [drm]] Adding all
current connectors for [CRTC:83:pipe C] to 00000000ae0f8d0f
[ 4.381236] [drm:drm_atomic_check_only [drm]] checking 00000000ae0f8d0f
[ 4.381243] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating
routing for [CONNECTOR:85:eDP-1]
[ 4.381247] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]]
[CONNECTOR:85:eDP-1] keeps [ENCODER:84:DDI A], now on [CRTC:47:pipe A]
[ 4.381251] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]]
[CRTC:47:pipe A] needs all connectors, enable: y, active: y
[ 4.381259] [drm:drm_atomic_add_affected_connectors [drm]] Adding all
current connectors for [CRTC:47:pipe A] to 00000000ae0f8d0f
[ 4.381267] [drm:drm_atomic_add_affected_planes [drm]] Adding all current
planes for [CRTC:47:pipe A] to 00000000ae0f8d0f
[ 4.381297] [drm:intel_atomic_check [i915]] [CONNECTOR:85:eDP-1] Limiting
display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36
[ 4.381325] [drm:intel_dp_compute_config [i915]] DP link computation with
max lane count 1 max rate 324000 max bpp 24 pixel clock 142520KHz
[ 4.381350] [drm:intel_dp_compute_config [i915]] Force DSC en = 0
[ 4.381373] [drm:intel_dp_compute_config [i915]] DP lane count 1 clock
324000 bpp 18
[ 4.381682] [drm:intel_dp_compute_config [i915]] DP link rate required
320670 available 324000
[ 4.381721] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 18,
dithering: 1
[ 4.381746] [drm:pipe_config_err [i915]] mismatch in dp_m_n (expected tu 64
gmch 4151195/4194304 link 172966/524288, or tu 0 gmch 0/0 link 0/0, found tu
64, gmch 4151195/4194304 link 230621/524288)
[ 4.381770] [drm:pipe_config_err [i915]] mismatch in pipe_bpp (expected 24,
found 18)
[ 4.381792] [drm:pipe_config_err [i915]] mismatch in port_clock (expected
432000, found 324000)
[ 4.381814] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe A][modeset]
[ 4.381836] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
[ 4.381856] [drm:intel_dump_pipe_config [i915]] output format: RGB
[ 4.381877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe
bpp: 18, dithering: 1
[ 4.381898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m:
4151195, gmch_n: 4194304, link_m: 230621, link_n: 524288, tu: 64
[ 4.381918] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
[ 4.381938] [drm:intel_dump_pipe_config [i915]] requested mode:
[ 4.381946] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080":
60 142520 1920 1968 2000 2080 1080 1083 1088 1142 0x48 0xa</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
<li>You are the QA Contact for the bug.</li>
<li>You are the assignee for the bug.</li>
</ul>
</body>
</html>