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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - Skylake GPU HANG while gstreamer H264 vaapi encoding from MJPEG vaapi decode on drm-tip"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110394#c38">Comment # 38</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - Skylake GPU HANG while gstreamer H264 vaapi encoding from MJPEG vaapi decode on drm-tip"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110394">bug 110394</a>
from <span class="vcard"><a class="email" href="mailto:chris@chris-wilson.co.uk" title="Chris Wilson <chris@chris-wilson.co.uk>"> <span class="fn">Chris Wilson</span></a>
</span></b>
<pre>(In reply to Andy Nicholas from <a href="show_bug.cgi?id=110394#c32">comment #32</a>)
<span class="quote">> This is the diff for the powergating test I'm running now. No other changes
> are made to the kernel, just this one patch:
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index eaf0793ebf60..29260ba32529 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8609,8 +8609,12 @@ static void intel_enable_rc6(struct drm_i915_private
> *dev_priv)
> cherryview_enable_rc6(dev_priv);
> else if (IS_VALLEYVIEW(dev_priv))
> valleyview_enable_rc6(dev_priv);
> - else if (INTEL_GEN(dev_priv) >= 9)
> - gen9_enable_rc6(dev_priv);
> + else if (INTEL_GEN(dev_priv) >= 9) {
> + gen9_disable_rc6(dev_priv);
> +
> + I915_WRITE(GEN9_PG_ENABLE,
> + GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
> + }
> else if (IS_BROADWELL(dev_priv))
> gen8_enable_rc6(dev_priv);
> else if (INTEL_GEN(dev_priv) >= 6)
>
>
> Btw -
>
> I did read through the gen9_enable_rc6() code and the "hysteresis" stuff
> jumped out at me. does anything bad happen if those calculations are not
> accurate?</span >
It will just use whatever the default values were. The important point here is
that with RC6_CONTROL=0 and PG_ENABLE!=0, we see exactly the same hang as
before. That is at least a nudge back towards the powergating as being the
culprit.</pre>
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