<html>
<head>
<base href="https://bugs.freedesktop.org/">
</head>
<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][RESUME] igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait - skip - Primary plane cannot be disabled separately from output, SKIP"
href="https://bugs.freedesktop.org/show_bug.cgi?id=110647">110647</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>[CI][RESUME] igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait - skip - Primary plane cannot be disabled separately from output, SKIP
</td>
</tr>
<tr>
<th>Product</th>
<td>DRI
</td>
</tr>
<tr>
<th>Version</th>
<td>DRI git
</td>
</tr>
<tr>
<th>Hardware</th>
<td>Other
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>medium
</td>
</tr>
<tr>
<th>Component</th>
<td>DRM/Intel
</td>
</tr>
<tr>
<th>Assignee</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>lakshminarayana.vudum@intel.com
</td>
</tr>
<tr>
<th>QA Contact</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr>
<tr>
<th>CC</th>
<td>intel-gfx-bugs@lists.freedesktop.org
</td>
</tr></table>
<p>
<div>
<pre><a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6052/re-icl-u/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6052/re-icl-u/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait.html</a>
Starting subtest: plane-primary-toggle-with-vblank-wait
Test requirement not met in function run_primary_test, file
../tests/kms_atomic_transition.c:69:
Test requirement: !(ret == -EINVAL)
Primary plane cannot be disabled separately from output
Last errno: 22, Invalid argument
Subtest plane-primary-toggle-with-vblank-wait: SKIP (6.288s)
Dmesg-Warnings
<3> [520.953781] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun
<3> [522.771336] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun
<3> [523.199836] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun
<3> [523.658894] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe B FIFO underrun
<3> [526.112734] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to start
channel equalization
<3> [526.283277] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe B FIFO underrun
<3> [526.530617] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe B FIFO underrun
<3> [527.006135] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe C FIFO underrun
<3> [527.627563] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe C FIFO underrun
<3> [528.458230] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe A FIFO underrun
<3> [528.471846] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU
pipe B FIFO underrun</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
<li>You are the assignee for the bug.</li>
<li>You are the QA Contact for the bug.</li>
</ul>
</body>
</html>