<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [CI][RESUME] igt@* - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO underrun" href="https://bugs.freedesktop.org/show_bug.cgi?id=111600#c4">Comment # 4</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [CI][RESUME] igt@* - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO underrun" href="https://bugs.freedesktop.org/show_bug.cgi?id=111600">bug 111600</a> from <a class="email" href="mailto:stanislav.lisovskiy@intel.com" title="Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>"> Stanislav Lisovskiy</a> <pre>I have looked and there seems to be no memory bandwidth check working for tgl, currently intel_max_data_rate function which is used for final comparation to accept/reject display configuration looks like this(with current drm-tip): if (IS_GEN(dev_priv, 11)) /* * FIXME with SAGV disabled maybe we can assume * point 1 will always be used? Seems to match * the behaviour observed in the wild. */ return min3(icl_max_bw(dev_priv, num_planes, 0), icl_max_bw(dev_priv, num_planes, 1), icl_max_bw(dev_priv, num_planes, 2)); else return UINT_MAX; There are other similar parts in intel_bw.c also. Once I modified those to query pcode and calculate bandwidth same way as for ICL, FIFO underruns disappeared. So my guess is that we are simply lacking bandwidth part here. Do we have any plans on enabling that bandwidth code for TGL?</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are on the CC list for the bug.</li> <li>You are the assignee for the bug.</li> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>