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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][SHARDS] igt@perf_pmu@busy-accuracy-98-vcs1- fail - Failed assertion: (double)(100.0 * busy_r) <= ((double)(100.0 * expected) + (2)) && (double)(100.0 * busy_r) >= ((double)(100.0 * expected) - (2))"
href="https://bugs.freedesktop.org/show_bug.cgi?id=111873#c2">Comment # 2</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][SHARDS] igt@perf_pmu@busy-accuracy-98-vcs1- fail - Failed assertion: (double)(100.0 * busy_r) <= ((double)(100.0 * expected) + (2)) && (double)(100.0 * busy_r) >= ((double)(100.0 * expected) - (2))"
href="https://bugs.freedesktop.org/show_bug.cgi?id=111873">bug 111873</a>
from <span class="vcard"><a class="email" href="mailto:cibuglog@gmail.com" title="CI Bug Log <cibuglog@gmail.com>"> <span class="fn">CI Bug Log</span></a>
</span></b>
<pre>A CI Bug Log filter associated to this bug has been updated:
{- TGL: igt@perf_pmu@busy-accuracy-* - fail - Failed assertion: (double)(100.0
* busy_r) <= ((double)(100.0 * expected) + (2)) && (double)(100.0 *
busy_r) >= ((double)(100.0 * expected) - (2)) -}
{+ TGL: igt@perf_pmu@busy-accuracy-* - fail - Failed assertion: (double)(100.0
* busy_r) <= ((double)(100.0 * expected) + (2)) && (double)(100.0 *
busy_r) >= ((double)(100.0 * expected) - (2)) +}
New failures caught by the filter:
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-tglb3/igt@perf_pmu@busy-accuracy-2-vcs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-tglb3/igt@perf_pmu@busy-accuracy-2-vcs0.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-tglb6/igt@perf_pmu@busy-accuracy-50-vecs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6980/shard-tglb6/igt@perf_pmu@busy-accuracy-50-vecs0.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-tglb1/igt@perf_pmu@busy-accuracy-50-vcs1.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6981/shard-tglb1/igt@perf_pmu@busy-accuracy-50-vcs1.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb2/igt@perf_pmu@busy-accuracy-50-vecs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb2/igt@perf_pmu@busy-accuracy-50-vecs0.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb4/igt@perf_pmu@busy-accuracy-2-bcs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb4/igt@perf_pmu@busy-accuracy-2-bcs0.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb5/igt@perf_pmu@busy-accuracy-50-vcs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb5/igt@perf_pmu@busy-accuracy-50-vcs0.html</a>
*
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb6/igt@perf_pmu@busy-accuracy-98-bcs0.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6982/shard-tglb6/igt@perf_pmu@busy-accuracy-98-bcs0.html</a></pre>
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